Mid Level Senior Asic Design Engineer Jobs
Mid level senior asic design engineer jobs call for engineers ready to own full chip design cycles, drive architectural decisions with limited oversight, and guide junior designers through implementation challenges. Openings are concentrated in Technology & Software, Electronics & Hardware, and Artificial Intelligence, with a mix of on-site, hybrid, and remote positions, and employers like NVIDIA, Apple, and Google hiring at this level now.
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Showing 5 of 73+ Mid Level Senior Asic Design Engineer jobs
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with design verification.
- Experience with SystemVerilog/Verilog.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 5 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based individual contributors (ICs) and chips.
- Experience in the full verification life-cycle from test planning to coverage closure.
- Experience with 2 or more SoC projects/cycles.
- Experience in verifying digital logic at RTL using SystemVerilog/UVM for ASICs.
- Familiarity with ASIC standard interfaces and memory system architecture.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an ASIC Design Verification Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design verification and silicon bring-up. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $138000 - $198000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with design verification.
- Experience with SystemVerilog/Verilog.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 5 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based individual contributors (ICs) and chips.
- Experience in the full verification life-cycle from test planning to coverage closure.
- Experience with 2 or more SoC projects/cycles.
- Experience in verifying digital logic at RTL using SystemVerilog/UVM for ASICs.
- Familiarity with ASIC standard interfaces and memory system architecture.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an ASIC Design Verification Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design verification and silicon bring-up. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $138000 - $198000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
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Find JobsMid Level Senior Asic Design Engineer Job Market
Who's Hiring
- NVIDIA15
- Apple7
- Google6
- Broadcom5
- Cisco3
Top Industries Hiring
- Technology & Software31
- Electronics & Hardware23
- Artificial Intelligence8
- Law & Legal Services5
- Aerospace & Defense3
Mid Level Senior Asic Design Engineer Jobs: Frequently Asked Questions
How do I get a mid level senior asic design engineer job?
Position yourself around ownership, not just contribution. Highlight projects where you drove RTL design, timing closure, or physical implementation from specification to tapeout with minimal supervision. Emphasize any cross-functional work with verification, physical design, or systems teams. Recruiters at this level want to see that you can carry a block or subsystem independently, not just execute tasks assigned by someone else.
Which companies hire mid level senior asic design engineers?
Companies hiring mid level senior asic design engineers right now include NVIDIA, Apple, and Google, based on current listings on Migrate Mate as of July 2026. Hiring at this level covers semiconductor manufacturers, fabless chip companies, and large technology firms building custom silicon for compute, networking, and consumer products.
Are there remote mid level senior asic design engineer jobs?
Yes, though on-site remains common given the toolchain and lab access many ASIC roles require. About 18% of mid level senior asic design engineer openings are remote or hybrid as of July 2026, with hybrid arrangements most common at companies where some design phases require physical presence but synthesis and verification work can be done remotely.
How do I move up to a mid level senior asic design engineer role?
The path from entry level centers on building demonstrable ownership across the full design flow. Early in your career, focus on mastering RTL coding and simulation, then take on complete block ownership, including timing constraints and sign-off. Delivering measurable results, such as meeting power-performance-area targets on a shipped product, combined with growing comfort in design reviews, signals readiness for mid level responsibilities.
Which industries hire the most mid level senior asic design engineers?
Mid Level senior asic design engineer roles concentrate in Technology & Software, Electronics & Hardware, and Artificial Intelligence, based on current listings on Migrate Mate as of July 2026. These sectors drive demand because they are actively building or scaling custom silicon for high-performance compute, communications infrastructure, and edge processing applications where off-the-shelf chips cannot meet their power or performance requirements.