Senior Level Senior Asic Design Engineer Jobs
Senior level senior asic design engineer jobs place experienced engineers in charge of complex chip architectures, full design cycles, and the cross-functional teams that bring silicon from concept to tape-out. Openings are concentrated across Electronics & Hardware, Technology & Software, and Artificial Intelligence, with a mix of on-site, hybrid, and remote positions available, and employers like Apple, NVIDIA, and Google hiring at this level now.
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with physical design and leading full-chip or massively intricate subchip implementation (e.g., from RTL2GDSII, including key stages like floorplanning, place and route, and timing closure) for high-speed ASICs in advanced process nodes.
- Experience in Python, Tcl, or Perl scripting.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with Cadence Innovus, Synopsys DP, Mentor Calibre, and StarRC, plus understanding of foundry technology files, rule decks, physical sign-off, and 2.5D/3D packaging.
- Technical leadership experience managing execution schedules, mitigating risks, and driving cross-functional collaboration with internal teams and external vendors.
- Understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
- Ability to navigate ambiguity, scale leadership across the physical design hierarchy, and excellent communication skills to articulate complex technical challenges to stakeholders.
About the job
Google’s Tensor Processing Units (TPUs) are incredibly complex, pushing the boundaries of physical design, power, and performance. In this role, you will provide technical leadership for the physical design of our next-generation AI silicon. Because of the sheer scale of our chips, our physical design leadership is highly dynamic; you will be expected to drive end-to-end execution with a scope that scales from owning highly complex, critical macro-subsystems up to overarching project-wide top-level implementation, depending on project needs.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Lead the physical design implementation and strategy for high-performance silicon, with leadership scope ranging from critical, high-complexity subchips to overarching top-level execution based on project phases and team needs.
- Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
- Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
- Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
- Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with physical design and leading full-chip or massively intricate subchip implementation (e.g., from RTL2GDSII, including key stages like floorplanning, place and route, and timing closure) for high-speed ASICs in advanced process nodes.
- Experience in Python, Tcl, or Perl scripting.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with Cadence Innovus, Synopsys DP, Mentor Calibre, and StarRC, plus understanding of foundry technology files, rule decks, physical sign-off, and 2.5D/3D packaging.
- Technical leadership experience managing execution schedules, mitigating risks, and driving cross-functional collaboration with internal teams and external vendors.
- Understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
- Ability to navigate ambiguity, scale leadership across the physical design hierarchy, and excellent communication skills to articulate complex technical challenges to stakeholders.
About the job
Google’s Tensor Processing Units (TPUs) are incredibly complex, pushing the boundaries of physical design, power, and performance. In this role, you will provide technical leadership for the physical design of our next-generation AI silicon. Because of the sheer scale of our chips, our physical design leadership is highly dynamic; you will be expected to drive end-to-end execution with a scope that scales from owning highly complex, critical macro-subsystems up to overarching project-wide top-level implementation, depending on project needs.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Lead the physical design implementation and strategy for high-performance silicon, with leadership scope ranging from critical, high-complexity subchips to overarching top-level execution based on project phases and team needs.
- Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
- Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
- Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
- Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.
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Find JobsSenior Level Senior Asic Design Engineer Job Market
Who's Hiring
- Apple15
- NVIDIA11
- Google6
- Broadcom5
- Synopsys5
Top Industries Hiring
- Electronics & Hardware47
- Technology & Software35
- Artificial Intelligence8
- Telecommunications7
- Law & Legal Services6
Senior Level Senior Asic Design Engineer Jobs: Frequently Asked Questions
How do I get a senior level senior asic design engineer job?
Employers at this level look for engineers who can own a design block or subsystem end to end, from microarchitecture through timing closure, without close supervision. A portfolio of successfully taped-out designs is the strongest signal. Experience driving design reviews, mentoring junior engineers, and collaborating with verification and physical design teams on schedule-driven programs gives candidates a clear edge over those with purely individual-contributor backgrounds.
Which companies hire senior level senior asic design engineers?
Companies hiring senior level senior asic design engineers right now include Apple, NVIDIA, and Google, based on current listings on Migrate Mate as of June 2026. Hiring at this level covers large semiconductor and systems companies building custom silicon, as well as hyperscalers and defense contractors investing in proprietary chip programs.
Are there remote senior level senior asic design engineer jobs?
Yes, though remote availability is more limited than in software disciplines given the lab and tooling requirements of hardware work. About 23% of senior level senior asic design engineer openings are remote or hybrid as of June 2026, with hybrid arrangements being the most common format at this seniority level.
What makes a senior asic design engineer role senior level?
Senior level roles carry ownership over significant design blocks or full subsystems rather than assigned tasks within a larger block. Engineers at this level make microarchitecture decisions, resolve timing and power trade-offs with minimal guidance, lead design reviews, and mentor early-career team members. The expectation is that they drive quality and schedule accountability, not just execute against a specification written by someone else.
Which industries hire the most senior level senior asic design engineers?
Senior level senior asic design engineer roles concentrate in Electronics & Hardware, Technology & Software, and Artificial Intelligence, based on current listings on Migrate Mate as of June 2026. These sectors drive hiring at this level because they are developing proprietary silicon for performance-critical applications where custom ASIC design offers advantages that off-the-shelf components cannot match.