Mid Level Senior Physical Design Engineer Jobs
Mid level senior physical design engineer jobs go to engineers ready to own physical design flows end to end, guide junior teammates, and make implementation decisions without constant oversight. Openings are spread across on-site, hybrid, and remote settings in Electronics & Hardware, Technology & Software, and Telecommunications, with employers like Apple, Qualcomm, and Intel hiring at this level now.
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Company:
Qualcomm Technologies, Inc.Job Area:
Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:
This individual leads, plans, synthesizes ambiguous or conflicting requirements and performs the complex responsibility of the Physical Design Flow of high-speed DDR, graphics, physical verification flows, micro-architecture, SOC algorithm design and modeling, and methodology, focusing on target power utilization and optimization for system-on-chip (SoC) products and how these features impact power and performance. Responsibilities include: Floor Planning, Clock Tree Synthesis, Place and Route, PDN, Timing analysis and closure. Performs various physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield) at the chip and block levels. Provides schedules and support cross-functional engineering effort to drive to signoff closure for tapeout. Acts as a strong contributor at design reviews and project meetings and communicates and implements a development plan.
Will accept a Master's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field and three (3) years of experience in a related occupation. Will also accept a Bachelor's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field and seven (7) years of progressive experience in a related occupation. Employer will accept any suitable combination of education, training or experience.
Pay Range: $161,179.00 - $210,000.00/year
Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
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EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
If you would like more information about this role, please contact Qualcomm Careers .
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Find JobsMid Level Senior Physical Design Engineer Job Market
Who's Hiring
- Apple28
- Qualcomm8
- Intel3

- NVIDIA3
- Astera Labs3

Top Industries Hiring
- Electronics & Hardware50
- Technology & Software15
- Telecommunications7
- Consulting & Professional Services6
- Retail3
Mid Level Senior Physical Design Engineer Jobs: Frequently Asked Questions
How do I get a mid level senior physical design engineer job?
Position yourself as an engineer who owns work independently, not one who needs close supervision. Highlight hands-on experience with place-and-route, timing closure, and physical verification on real tapeouts. Show that you can take a block or subsystem from floorplan through signoff with minimal guidance. Emphasize any cross-functional collaboration with design, verification, or packaging teams, since hiring managers at this level want engineers who operate across the full flow.
Which companies hire mid level senior physical design engineers?
Companies hiring mid level senior physical design engineers right now include Apple, Qualcomm, and Intel, based on current listings on Migrate Mate as of July 2026. Hiring at this level comes from a broad mix of semiconductor companies, fabless chip designers, EDA tool vendors, and defense electronics firms that run active ASIC or SoC development programs.
Are there remote mid level senior physical design engineer jobs?
Yes, though physical design work skews more on-site than many engineering disciplines because of tool licensing infrastructure and lab access. About 13% of mid level senior physical design engineer openings are remote or hybrid as of July 2026, so options exist if flexibility matters to you. Hybrid arrangements tied to specific tapeout milestones are common at this level.
How do I move up to a mid level senior physical design engineer role?
The path from entry level to mid level in physical design is built on completing full tapeout cycles and taking ownership of increasingly complex blocks. Engineers who progress deepened their skills in static timing analysis, power grid design, and physical verification while moving from assisted execution to independent delivery. Demonstrating measurable impact, such as resolving a critical timing path or reducing die area, signals readiness for mid level responsibility.
Which industries hire the most mid level senior physical design engineers?
Mid Level senior physical design engineer roles concentrate in Electronics & Hardware, Technology & Software, and Telecommunications, based on current listings on Migrate Mate as of July 2026. Those sectors drive hiring because they run continuous ASIC and SoC development cycles that require engineers who can own design implementation at the block and chip level without heavy senior oversight on every decision.