SoC Physical Design Engineer Jobs
SoC Physical Design Engineer jobs are open from new-grad to principal across semiconductor companies, fabless chip startups, and consumer electronics firms, with specializations in floorplanning, timing closure, and power delivery network design. Find a role that fits below and apply directly.
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Top stateCalifornia
Top employerApple
Top citySan Diego, CA
Work type81% On-site
Top industryElectronics
Showing 5 of 112+ SoC Physical Design Engineer jobs
HBM SoC Physical Design Engineer
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Added 1d ago
Micron Technology
HBM SoC Physical Design Engineer
Folsom, California
Added 1d ago
SoC Physical Design Formal Verification Engineer, HBM
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Added 1d ago
Micron Technology
SoC Physical Design Formal Verification Engineer, HBM
Folsom, California
Added 1d ago
Senior SoC Design Engineer
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Added 2d ago
Microsoft
Senior SoC Design Engineer
Redmond, Washington
Added 2d ago
Executive Director SOC Physical Design
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Added 2d ago
Synopsys
Executive Director SOC Physical Design
Sunnyvale, California
Added 2d ago
Senior Principal Digital SoC Design Engineer
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Added 2d ago
MaxLinear Inc.
Senior Principal Digital SoC Design Engineer
San Jose, California
Added 2d ago
Added 1d ago
HBM SoC Physical Design Engineer
Micron Technology·Folsom, California
Job functions:
$146k - $247k/yr
Bachelor's degree in electrical engineering
10,000+ employees
Job Description
Job ID
JR107315
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies.
Key Responsibilities
Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity.
Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule.
Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements.
Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.
Required Qualifications
Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
Preferred Qualifications
Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
Minimum 3 years of experience in a related field.
Proven ability to mentor and develop engineers early in their careers.
Good understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$146,000.00 - $247,000.00 a year
Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
Micron Foundation
Strong communities and education are vital to the success of both society and innovative companies. Every Micron site understands the complex needs of their local community. Whether it’s through strategic giving, sponsorships or deploying team member volunteers, we are making a difference.
Sustainability
Micron is committed to sustainable practices and supporting our global community. We are building and maintaining sustainable operations, products, and communities while focusing on opportunities and risks that are most important to our business success and stakeholders.
Insights from previous hires
Years of experience
< 2
8+
Less than 2 years
2 - 4 years
4 - 8 years
8+ years
Top skills
Cadence Tools
Algorithms
C++
Previously worked at
I
T
Q
Previously worked as
1. Principal Engineer
2. Senior Engineer
3. Lead Engineer
4. Senior Design Engineer
5. Senior Principal Engineer
JR107315
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies.
Key Responsibilities
Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity.
Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule.
Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements.
Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.
Required Qualifications
Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
Preferred Qualifications
Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
Minimum 3 years of experience in a related field.
Proven ability to mentor and develop engineers early in their careers.
Good understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$146,000.00 - $247,000.00 a year
Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
Micron Foundation
Strong communities and education are vital to the success of both society and innovative companies. Every Micron site understands the complex needs of their local community. Whether it’s through strategic giving, sponsorships or deploying team member volunteers, we are making a difference.
Sustainability
Micron is committed to sustainable practices and supporting our global community. We are building and maintaining sustainable operations, products, and communities while focusing on opportunities and risks that are most important to our business success and stakeholders.
Insights from previous hires
Years of experience
< 2
8+
Less than 2 years
2 - 4 years
4 - 8 years
8+ years
Top skills
Cadence Tools
Algorithms
C++
Previously worked at
I
T
Q
Previously worked as
1. Principal Engineer
2. Senior Engineer
3. Lead Engineer
4. Senior Design Engineer
5. Senior Principal Engineer
Micron Technology
HBM SoC Physical Design Engineer
Folsom, California
Added 1d ago10,000+ employees
Job functions:
$146k - $247k/yr
Bachelor's degree in electrical engineering
Job Description
Job ID
JR107315
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies.
Key Responsibilities
Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity.
Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule.
Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements.
Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.
Required Qualifications
Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
Preferred Qualifications
Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
Minimum 3 years of experience in a related field.
Proven ability to mentor and develop engineers early in their careers.
Good understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$146,000.00 - $247,000.00 a year
Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
Micron Foundation
Strong communities and education are vital to the success of both society and innovative companies. Every Micron site understands the complex needs of their local community. Whether it’s through strategic giving, sponsorships or deploying team member volunteers, we are making a difference.
Sustainability
Micron is committed to sustainable practices and supporting our global community. We are building and maintaining sustainable operations, products, and communities while focusing on opportunities and risks that are most important to our business success and stakeholders.
Insights from previous hires
Years of experience
< 2
8+
Less than 2 years
2 - 4 years
4 - 8 years
8+ years
Top skills
Cadence Tools
Algorithms
C++
Previously worked at
I
T
Q
Previously worked as
1. Principal Engineer
2. Senior Engineer
3. Lead Engineer
4. Senior Design Engineer
5. Senior Principal Engineer
JR107315
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies.
Key Responsibilities
Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity.
Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule.
Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements.
Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.
Required Qualifications
Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
Preferred Qualifications
Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
Minimum 3 years of experience in a related field.
Proven ability to mentor and develop engineers early in their careers.
Good understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$146,000.00 - $247,000.00 a year
Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
Micron Foundation
Strong communities and education are vital to the success of both society and innovative companies. Every Micron site understands the complex needs of their local community. Whether it’s through strategic giving, sponsorships or deploying team member volunteers, we are making a difference.
Sustainability
Micron is committed to sustainable practices and supporting our global community. We are building and maintaining sustainable operations, products, and communities while focusing on opportunities and risks that are most important to our business success and stakeholders.
Insights from previous hires
Years of experience
< 2
8+
Less than 2 years
2 - 4 years
4 - 8 years
8+ years
Top skills
Cadence Tools
Algorithms
C++
Previously worked at
I
T
Q
Previously worked as
1. Principal Engineer
2. Senior Engineer
3. Lead Engineer
4. Senior Design Engineer
5. Senior Principal Engineer
SoC Physical Design Engineer Jobs by Experience Level
See All 112+ SoC Physical Design Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
Find JobsSoC Physical Design Engineer Job Market
Who's Hiring
- Apple62
- Meta8
- Qualcomm8
- Micron Technology5
- Velaura2V
Top Industries Hiring
- Electronics & Hardware
- Technology & Software
What Employers Look For
The qualifications that appear most often in SoC physical design engineer jobs.
- Bachelor's or master's degree in electrical engineering, computer engineering, or a related field
- Hands-on experience with EDA tools such as Cadence Innovus, Synopsys ICC2, or Mentor Calibre
- Proficiency in static timing analysis using PrimeTime or equivalent signoff tools
- Experience with physical verification including DRC, LVS, and antenna rule checks
- Familiarity with advanced process nodes at 28nm or below and associated PDK constraints
- Scripting skills in Tcl, Python, or Perl for flow automation and design exploration
Tips for Your SoC Physical Design Engineer Job Search
Tailor your resume to each node
Hiring managers scan for the specific process node you've taped out on. Call out your most advanced node prominently, whether that's 7nm, 5nm, or 3nm, and list the corresponding PDK and signoff tools you used on that project.
Quantify timing closure results
Generic claims about 'meeting timing' won't stand out. State the slack you closed, the number of paths fixed, or the frequency milestone you hit. Concrete numbers from your most recent tapeout give recruiters a real signal fast.
Apply early to roles that fit
Migrate Mate lists soc physical design engineer openings from across the United States in one place, so you can find roles that match and apply directly to each listing.
Target job descriptions by tool stack
Filter openings by the EDA tools named in the job description. If you're strong in Cadence Innovus, prioritize those listings over Synopsys ICC2 postings. Tool fluency is often the first screen, and a mismatch wastes everyone's time.
Prepare a tapeout story for interviews
Most soc physical design engineer interviews include a deep dive on one tapeout you owned. Prepare a concise walkthrough covering the chip's purpose, your specific ownership area, the hardest physical constraint you faced, and how you resolved it.
Negotiate against competing offers strategically
If you have more than one offer, disclose that you're evaluating options without naming the competing company. Ask each hiring manager what flexibility exists on sign-on or equity, since base adjustments in this role are often constrained by internal band structures.
SoC Physical Design Engineer Jobs: Frequently Asked Questions
Which companies are hiring the most soc physical design engineers?
Apple, Meta, and Qualcomm are hiring the most soc physical design engineers right now, with openings concentrated in California, Texas, and Oregon, based on current listings on Migrate Mate as of November 2026. Demand is especially strong at fabless semiconductor companies developing custom silicon for AI, mobile, and networking applications.
How many soc physical design engineer jobs are remote?
About 19% of soc physical design engineer openings are fully remote or hybrid as of November 2026, reflecting the lab-dependent nature of much of the work. Sub-areas closest to remote-friendly arrangements tend to involve floorplan exploration, scripting, and timing analysis rather than hands-on lab bring-up or PDK development.
How do you become a soc physical design engineer?
Start with a bachelor's degree in electrical or computer engineering, with coursework covering VLSI design, digital circuits, and semiconductor devices. Build hands-on fluency in at least one major EDA tool suite through academic projects or an internship. Progress through roles in physical verification, place and route, or backend design, then deepen expertise in timing closure and power grid analysis as you take on full chip ownership responsibilities.
Can you get a soc physical design engineer job with little experience?
Entry-level roles do exist, particularly at larger EDA vendors and semiconductor companies that run structured new-grad programs focused on backend flows. The strongest candidates without industry tapeout experience come in with a university chip project, demonstrated tool proficiency in Cadence or Synopsys environments, and scripting skills. Contract positions and internships at IP companies are also practical starting points when direct full-time openings are competitive.
What does the soc physical design engineer interview process look like?
Most processes begin with a recruiter screen followed by a technical phone interview covering place-and-route concepts, timing analysis fundamentals, and your experience with specific EDA tools. A take-home exercise or coding screen testing Tcl or Python scripting is common at mid-stage. Final rounds typically include a panel of physical design engineers asking detailed questions about a tapeout you owned, plus a cross-functional discussion with the hiring manager on team fit and project scope.
Where can I find and apply to soc physical design engineer jobs?
You can find and apply to soc physical design engineer jobs on Migrate Mate, which lists current openings from across the United States. The listings cover roles at every seniority level across semiconductor companies, fabless startups, and consumer electronics firms. Find roles that fit your background and apply directly to each listing.
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