STEM OPT Design Verification Jobs
Design Verification roles in semiconductors, embedded systems, and hardware engineering are a strong fit for STEM OPT students with degrees in electrical engineering, computer engineering, or computer science. Your 24-month STEM OPT extension applies here, and every employer you work for must be enrolled in E-Verify.
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Get Access To All JobsSUMMARY
At Apple, we work every single day to craft products that enrich people's lives! Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining our group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices! In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC.
DESCRIPTION
- As a member of our physical design team, you will perform various types of physical verification checks such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography at the chip and block level.
- You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.
- You will lead schedules and support cross-functional engineering efforts.
- You will work on padring, bump, RDL design, and working with the package and floorplan teams.
MINIMUM QUALIFICATIONS
- BS degree with 0 years of relevant industry experience.
PREFERRED QUALIFICATIONS
- Experienced with physical verification flows such as DRC/LVS/ANT and layout integration methodology
- Understands RTL to GDS physical design flow
- Scripting skills to debug flow related issues and make enhancements as appropriate
- Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc
- Layout design background and experience a plus
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
Apple accepts applications to this posting on an ongoing basis.
SUMMARY
At Apple, we work every single day to craft products that enrich people's lives! Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining our group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices! In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC.
DESCRIPTION
- As a member of our physical design team, you will perform various types of physical verification checks such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography at the chip and block level.
- You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.
- You will lead schedules and support cross-functional engineering efforts.
- You will work on padring, bump, RDL design, and working with the package and floorplan teams.
MINIMUM QUALIFICATIONS
- BS degree with 0 years of relevant industry experience.
PREFERRED QUALIFICATIONS
- Experienced with physical verification flows such as DRC/LVS/ANT and layout integration methodology
- Understands RTL to GDS physical design flow
- Scripting skills to debug flow related issues and make enhancements as appropriate
- Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc
- Layout design background and experience a plus
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
Apple accepts applications to this posting on an ongoing basis.
See all 75+ STEM OPT Design Verification Jobs
Sign up for free to unlock all listings, filter by visa type, and get alerts for new STEM OPT Design Verification Jobs.
Get Access To All JobsTips for Finding STEM OPT Authorization in Design Verification
Confirm your CIP code covers verification roles
Check that your degree's Classification of Instructional Programs code maps to an approved STEM field before applying. Electrical Engineering (14.1001) and Computer Engineering (14.0901) both qualify, but a mismatch delays your extension.
Search employers through E-Verify before applying
Use the E-Verify employer search to confirm a company is enrolled before you invest time in their process. Design Verification roles often sit inside hardware or silicon teams at companies that don't always advertise their E-Verify status publicly.
Build your I-983 training plan around functional verification
Your I-983 must list specific learning objectives tied to your role. For Design Verification, name concrete skills: writing UVM testbenches, coverage closure, formal property verification, or RTL debugging, not vague goals like 'gain industry experience.'
Target companies with active USCIS LCA filings in EE roles
Migrate Mate surfaces employers with verified Labor Condition Application filing history in electrical and computer engineering occupations, so you can focus your search on companies already set up to hire STEM OPT candidates in technical hardware roles.
Request an offer letter that specifies your direct supervisor
USCIS requires a bona fide employer-employee relationship for STEM OPT. Your offer letter should name your direct reporting manager and describe hands-on training, not just a job title, to support your DSO's I-983 sign-off without delays.
Apply 90 days before your OPT end date to avoid a gap
Your DSO must recommend the STEM OPT extension in SEVIS before your initial OPT expires. Filing your I-765 at least 90 days out keeps you in a valid cap-gap period if USCIS processing extends past your OPT end date.
Frequently Asked Questions
Does a Design Verification role qualify for the STEM OPT extension?
Yes, if your employer is enrolled in E-Verify and your degree is in an approved STEM field such as Electrical Engineering, Computer Engineering, or Computer Science. The O*NET occupation profile for Design Verification engineers confirms the role's alignment with STEM disciplines. Your DSO verifies the CIP code match before recommending the extension in SEVIS.
What should my I-983 training plan include for a Design Verification job?
Your I-983 must document specific learning goals tied to your actual work. For Design Verification, that means naming technical skills you'll develop, such as UVM methodology, SystemVerilog assertions, simulation debugging, or coverage-driven verification. Generic objectives like 'improve engineering skills' won't satisfy USCIS. Your employer's designated training supervisor must sign the form and provide mid-point and final evaluations.
How do I confirm my employer is enrolled in E-Verify before accepting an offer?
E-Verify maintains a public employer search tool where you can look up a company by name or location. Enrollment is required for all STEM OPT employers, so confirm this before signing an offer letter. Semiconductor and hardware design firms with federal contracts are typically already enrolled, but smaller IP or EDA startups may not be, so always verify directly.
Can I work for multiple employers on STEM OPT in a Design Verification role?
Yes, but each employer must be separately enrolled in E-Verify, and you need a separate I-983 training plan for each one. Your DSO must be notified of every employer relationship. A part-time verification contract role at a second company counts as concurrent employment and requires its own documentation. USCIS expects all training to be directly related to your qualifying STEM degree.
Where can I find Design Verification jobs where employers are already set up for STEM OPT?
Migrate Mate filters Design Verification roles by employers with active E-Verify enrollment and LCA filing history in engineering occupations, so you're not applying blind to companies that have never hired on STEM OPT before. This saves the back-and-forth of asking HR whether they can take on a STEM OPT student for a hardware verification position.