DFT Engineer Jobs in USA with Visa Sponsorship
DFT Engineer roles at U.S. semiconductor and EDA companies qualify as specialty occupations under H-1B visa, making employer sponsorship the standard path for international candidates. Employers file a Labor Condition Application with DOL before petitioning USCIS, and the H-1B is subject to an annual cap and selection process.
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DFT Engineer for ASIC/Chip level ATPG
Broadcom's ASIC Product Division is seeking candidates for a DFT position at our Fort Collins, Colorado, Development Center. The successful candidate will lead DFT programs from chip-level specification through implementation, verification, and product release to production.
The candidate will participate in all phases of SoC DFT activities for Broadcom APD (ASIC Products Division) designs, including DFT architecture, test insertion, verification, pattern generation, coverage improvement, post-silicon debug, and yield improvement to meet product test metrics. Responsibilities also include collaborating with physical design and STA teams for DFT-mode timing closure and directly interfacing with external customers.
Responsibilities:
- Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC.
- Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration.
- Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns.
- Collaborate closely with STA and design integration engineers for timing and design closure.
- Generate, verify, and debug test vectors prior to tapeout release.
- Validate and debug test vectors on ATE during silicon bring-up.
- Assist with silicon failure analysis, diagnostics, and yield improvement efforts.
- Interface with customers, physical design teams, and global test engineering/manufacturing teams.
- Work closely with IP DFT engineers and cross-functional stakeholders.
- Debug customer-returned parts (RMA) on ATE.
- Proficiency in scripting and automation (such as Python, TCL, or C++), with an emphasis on applying AI-augmented development to streamline test flows.
- Develop innovative DFT solutions for advanced process nodes (3nm and beyond).
- Automate DFT and test vector generation flows.
Skills/Experience:
- Strong DFT architecture and implementation background (Scan, BIST, IO/Analog DFT, IJTAG/IEEE 1687, IEEE 1149.1/1149.6)
- Proficiency with EDA tools for scan insertion, compression, and ATPG (e.g., DFT Compiler, TestKompress, TetraMax, FastScan)
- Hands-on experience with memory and logic BIST strategies, verification, and debug across embedded memories (SRAM, CAM, RF, ROM)
- Experience with In-Field testing solutions a plus
- Extensive experience in Verilog coding, testbench development, ATPG pattern generation, simulation, and timing constraints/Test-STA
- Solid foundation in digital/analog circuit design, device physics, silicon manufacturing, synthesis, and transistor reliability
- Strong problem-solving, root-cause debug, statistical process control, and data analysis skills for silicon yield and quality improvement
- Effective cross-functional communication and project management skills to collaborate across physical design, test engineering, and operations
- Experience with ATE silicon bring-up, debug, and high-speed IP/interface testing (SerDes, DDR, PCIe, Ethernet, CXL, Tessent SSN) is a plus
Education & Experience:
Bachelors in Electrical/Electronic/Computer Engineering and 8+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 6+ years of relevant industry experience
Compensation and Benefits
The annual base salary range for this position is USD 109,700.00 To USD 175,500.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Job Description:
DFT Engineer for ASIC/Chip level ATPG
Broadcom's ASIC Product Division is seeking candidates for a DFT position at our Fort Collins, Colorado, Development Center. The successful candidate will lead DFT programs from chip-level specification through implementation, verification, and product release to production.
The candidate will participate in all phases of SoC DFT activities for Broadcom APD (ASIC Products Division) designs, including DFT architecture, test insertion, verification, pattern generation, coverage improvement, post-silicon debug, and yield improvement to meet product test metrics. Responsibilities also include collaborating with physical design and STA teams for DFT-mode timing closure and directly interfacing with external customers.
Responsibilities:
- Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC.
- Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration.
- Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns.
- Collaborate closely with STA and design integration engineers for timing and design closure.
- Generate, verify, and debug test vectors prior to tapeout release.
- Validate and debug test vectors on ATE during silicon bring-up.
- Assist with silicon failure analysis, diagnostics, and yield improvement efforts.
- Interface with customers, physical design teams, and global test engineering/manufacturing teams.
- Work closely with IP DFT engineers and cross-functional stakeholders.
- Debug customer-returned parts (RMA) on ATE.
- Proficiency in scripting and automation (such as Python, TCL, or C++), with an emphasis on applying AI-augmented development to streamline test flows.
- Develop innovative DFT solutions for advanced process nodes (3nm and beyond).
- Automate DFT and test vector generation flows.
Skills/Experience:
- Strong DFT architecture and implementation background (Scan, BIST, IO/Analog DFT, IJTAG/IEEE 1687, IEEE 1149.1/1149.6)
- Proficiency with EDA tools for scan insertion, compression, and ATPG (e.g., DFT Compiler, TestKompress, TetraMax, FastScan)
- Hands-on experience with memory and logic BIST strategies, verification, and debug across embedded memories (SRAM, CAM, RF, ROM)
- Experience with In-Field testing solutions a plus
- Extensive experience in Verilog coding, testbench development, ATPG pattern generation, simulation, and timing constraints/Test-STA
- Solid foundation in digital/analog circuit design, device physics, silicon manufacturing, synthesis, and transistor reliability
- Strong problem-solving, root-cause debug, statistical process control, and data analysis skills for silicon yield and quality improvement
- Effective cross-functional communication and project management skills to collaborate across physical design, test engineering, and operations
- Experience with ATE silicon bring-up, debug, and high-speed IP/interface testing (SerDes, DDR, PCIe, Ethernet, CXL, Tessent SSN) is a plus
Education & Experience:
Bachelors in Electrical/Electronic/Computer Engineering and 8+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 6+ years of relevant industry experience
Compensation and Benefits
The annual base salary range for this position is USD 109,700.00 To USD 175,500.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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Get Access To All JobsTips for Finding Visa Sponsorship as a DFT Engineer
Align your degree field precisely
DFT engineering requires a directly related specialty occupation degree. A computer engineering or electrical engineering degree maps cleanly, but a general physics degree may draw an RFE. Document any graduate coursework in VLSI, digital logic, or scan-chain design to strengthen the specialty occupation argument.
Target fabless and IDM employers by filing history
Semiconductor companies like fabless chip designers and integrated device manufacturers file LCAs under specific job titles. Search the OFLC Wage Search for 'Design Verification Engineer' and 'DFT Engineer' to identify which employers certify these roles consistently and are actively hiring sponsorship candidates.
Find verified DFT sponsoring employers on Migrate Mate
Migrate Mate lists U.S. employers with verified LCA sponsorship history for DFT and related semiconductor roles, searchable by location and job type. Use it to focus your applications on companies that have already committed to the filing process for this occupation.
Clarify ATPG tool expertise in your resume
Employers filing an LCA must justify the specialty occupation to DOL. DFT-specific skills like Tessent, Synopsys DFT Compiler, or boundary-scan experience signal a narrower, degree-required discipline. Generic 'verification engineer' framing can complicate the specialty occupation determination during USCIS adjudication.
Confirm LCA certification before signing an offer
Your employer must file and receive a certified LCA from DOL before submitting the H-1B petition to USCIS. Verify that the LCA job title and wage level match your offer letter exactly. Mismatches between the LCA and I-129 petition are a leading cause of Requests for Evidence in DFT petitions.
Understand TN eligibility if you hold Canadian or Mexican citizenship
TN status covers 'engineer' roles under the USMCA list, but the position must require an engineering degree in a directly related field. DFT engineering typically satisfies this if your employer documents the degree requirement clearly. TN has no annual cap and no lottery, unlike H-1B.
Frequently Asked Questions
Does a DFT Engineer role qualify as a specialty occupation for H-1B?
Yes. DFT engineering requires theoretical and practical application of highly specialized knowledge in areas like scan insertion, ATPG, and boundary-scan testing, with a minimum of a bachelor's degree in electrical engineering, computer engineering, or a closely related field. USCIS evaluates specialty occupation on a case-by-case basis, so your employer's LCA and I-129 petition should explicitly document the degree requirement for the specific DFT role.
Which visa types are available for international DFT Engineers in the U.S.?
H-1B is the primary path and covers specialty occupation roles like DFT engineering. Canadian and Mexican nationals can use TN visa status under the USMCA engineer category with no cap or lottery. Australian nationals may qualify for the E-3 visa, which also requires a specialty occupation and a Labor Condition Application filed by the employer.
How do I find U.S. employers who sponsor DFT Engineers?
Migrate Mate lists U.S. employers with verified sponsorship history for DFT and semiconductor engineering roles. Focus your search on fabless semiconductor companies, integrated device manufacturers, and EDA tool vendors, as these segments file LCAs for DFT-specific positions most consistently.
Can a master's degree in a related field strengthen a DFT Engineer H-1B petition?
Yes. A master's degree in electrical engineering, computer engineering, or computer science directly reinforces the specialty occupation argument and may also make you eligible for the H-1B advanced degree exemption, which provides an additional 20,000 cap-exempt slots annually. Your employer should reference your graduate coursework in VLSI design or digital systems in the supporting documentation submitted to USCIS.
What happens to my H-1B status if I switch employers while working as a DFT Engineer?
H-1B portability allows you to start with a new employer once the new petition is filed with USCIS, without waiting for approval, as long as you're maintaining valid H-1B status. Your new employer must file a fresh I-129 petition and a certified LCA with DOL that reflects the specific DFT role, wage level, and work location before you begin the new position.
What is the prevailing wage requirement for sponsored DFT Engineer jobs?
U.S. employers sponsoring a visa must pay at least the prevailing wage, which is what workers in the same role, area, and experience level typically earn. The Department of Labor sets this rate to make sure companies aren't hiring foreign workers simply because they'd accept lower pay than a U.S. worker. It varies by job title, location, and experience. You can look up current prevailing wage rates for any occupation and location using the OFLC Wage Search page.