Senior Physical Design Engineer Jobs in USA with Visa Sponsorship
Senior Physical Design Engineer roles attract strong H-1B sponsorship from semiconductor companies like Qualcomm, Intel, NVIDIA, and Apple. The work qualifies as a specialty occupation requiring an advanced degree in electrical engineering or a closely related field, making visa approval rates high for qualified candidates. For detailed occupation requirements, see the O*NET profile.
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Get Access To All JobsINTRODUCTION
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. Join NVIDIA and become part of a team advancing the frontiers of AI technology!
ROLE AND RESPONSIBILITIES
As we lead innovation in AI and accelerated computing, we seek a Senior Physical Design Engineer to contribute to our outstanding progress in chip design. At NVIDIA, you’ll collaborate with extraordinary talent and thrive in an environment that values diversity, collaboration, and remarkable accomplishments.
What You'll Be Doing
In the role of a Senior Physical Design Engineer, you will play a crucial role in our innovative LPU chip design.
- Full-Flow Ownership: Responsible for Synthesis, floorplanning, place & route, timing constraints, UPF and LEC at the block/partition level and top level.
- Cross-Functional Optimization: Partner with IP, Front-End logic design and Architecture teams to streamline IP integration, drive PPA (Power, Performance, Area) optimizations, resolving architectural bottlenecks to enable efficient physical implementation.
- Tapeout Execution: Lead design closure in collaboration with IP, PnR, Sign-off teams, ensuring 100% verification compliance for successful GDSII handoff and tapeout.
- Methodology Innovation: Architect data-driven EDA flows and methodologies in collaboration with CAD teams, implementing automated enhancements that measurably improve PPA and design cycle efficiency.
BASIC QUALIFICATIONS
- B.S. in Electrical/Computer Engineering or equivalent experience (M.S./Ph.D. preferred) with 5+ years of industry experience delivering full-flow physical design for large-scale, high-performance SoCs at advanced process nodes.
- Full-Flow Execution: Proven track record of driving designs through the complete RTL-to-GDSII flow, including synthesis, placement, CTS, routing, extraction, and physical/electrical verification.
- Low-Power Expertise: Deep understanding of low-power design intent (UPF/CPF), formal equivalency checks (LEC), and rule verification for complex multi-voltage domain architectures.
- Clock & Timing Mastery: Expert-level proficiency in advanced CTS methodologies, clock tree synthesis, and sign-off timing analysis (MCMM STA) using complex constraints.
- PPA Optimization: Demonstrated ability to implement aggressive power, performance and area optimization techniques, and identify reduction opportunities across the entire physical design cycle.
- Sign-off & Integrity: Strong command of power grid design, EMIR analysis, and ECO generation to ensure robust silicon integrity and timing closure.
- DFT & Block-Level Integration: Skilled in employing best-known methods to optimize and handle DFT structures within block-level physical design implementations.
- EDA Tool Proficiency: Expert-level command of industry-standard tool suites for end-to-end physical design flows.
- Automation & Innovation: Proficient in scripting (TCL, Python, Perl) to automate flows, with a forward-looking ability to integrate AI-driven optimizations for enhanced design efficiency.
- High-Speed IP Integration: Specialized experience in the physical design of blocks and partitions containing high-speed SerDes IPs, such as PCIe, CXL, C2C, and Die-to-Die interfaces a plus.
COMPENSATION
- Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until March 16, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
JR2014642
INTRODUCTION
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. Join NVIDIA and become part of a team advancing the frontiers of AI technology!
ROLE AND RESPONSIBILITIES
As we lead innovation in AI and accelerated computing, we seek a Senior Physical Design Engineer to contribute to our outstanding progress in chip design. At NVIDIA, you’ll collaborate with extraordinary talent and thrive in an environment that values diversity, collaboration, and remarkable accomplishments.
What You'll Be Doing
In the role of a Senior Physical Design Engineer, you will play a crucial role in our innovative LPU chip design.
- Full-Flow Ownership: Responsible for Synthesis, floorplanning, place & route, timing constraints, UPF and LEC at the block/partition level and top level.
- Cross-Functional Optimization: Partner with IP, Front-End logic design and Architecture teams to streamline IP integration, drive PPA (Power, Performance, Area) optimizations, resolving architectural bottlenecks to enable efficient physical implementation.
- Tapeout Execution: Lead design closure in collaboration with IP, PnR, Sign-off teams, ensuring 100% verification compliance for successful GDSII handoff and tapeout.
- Methodology Innovation: Architect data-driven EDA flows and methodologies in collaboration with CAD teams, implementing automated enhancements that measurably improve PPA and design cycle efficiency.
BASIC QUALIFICATIONS
- B.S. in Electrical/Computer Engineering or equivalent experience (M.S./Ph.D. preferred) with 5+ years of industry experience delivering full-flow physical design for large-scale, high-performance SoCs at advanced process nodes.
- Full-Flow Execution: Proven track record of driving designs through the complete RTL-to-GDSII flow, including synthesis, placement, CTS, routing, extraction, and physical/electrical verification.
- Low-Power Expertise: Deep understanding of low-power design intent (UPF/CPF), formal equivalency checks (LEC), and rule verification for complex multi-voltage domain architectures.
- Clock & Timing Mastery: Expert-level proficiency in advanced CTS methodologies, clock tree synthesis, and sign-off timing analysis (MCMM STA) using complex constraints.
- PPA Optimization: Demonstrated ability to implement aggressive power, performance and area optimization techniques, and identify reduction opportunities across the entire physical design cycle.
- Sign-off & Integrity: Strong command of power grid design, EMIR analysis, and ECO generation to ensure robust silicon integrity and timing closure.
- DFT & Block-Level Integration: Skilled in employing best-known methods to optimize and handle DFT structures within block-level physical design implementations.
- EDA Tool Proficiency: Expert-level command of industry-standard tool suites for end-to-end physical design flows.
- Automation & Innovation: Proficient in scripting (TCL, Python, Perl) to automate flows, with a forward-looking ability to integrate AI-driven optimizations for enhanced design efficiency.
- High-Speed IP Integration: Specialized experience in the physical design of blocks and partitions containing high-speed SerDes IPs, such as PCIe, CXL, C2C, and Die-to-Die interfaces a plus.
COMPENSATION
- Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until March 16, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
JR2014642
How to Get Visa Sponsorship as a Senior Physical Design Engineer
Target semiconductor and fabless chip companies first
Companies like Qualcomm, NVIDIA, Intel, and Broadcom file hundreds of H-1B petitions for physical design roles annually. Their established immigration processes make sponsorship faster and more predictable than pursuing smaller startups without dedicated legal teams.
Align your degree field with the job description
USCIS requires a direct relationship between your degree and the role. A degree in electrical engineering, computer engineering, or VLSI design maps cleanly to physical design work. A general computer science degree may require supporting documentation to establish specialty occupation status.
Highlight tool expertise in your resume
Proficiency in Cadence Innovus, Synopsys ICC2, or Mentor Calibre signals genuine specialty and strengthens the employer's H-1B petition. Documented experience with advanced process nodes like 5nm or 3nm further supports the specialty occupation argument during USCIS review.
Understand the cap-exempt employer advantage
Universities and affiliated research labs are exempt from the H-1B lottery. If you hold a U.S. master's or PhD in electrical engineering, cap-exempt employers offer a sponsorship path that bypasses lottery uncertainty entirely while you build U.S. industry experience.
Ask about O-1A eligibility if you have strong credentials
Senior engineers with publications, patents, conference presentations, or awards from institutions like IEEE may qualify for the O-1A visa. It has no lottery, no annual cap, and is employer-sponsored, making it a strong H-1B alternative for high-achieving candidates.
Use Migrate Mate to find employers actively sponsoring
Not every company advertising physical design roles will sponsor visas. Migrate Mate filters specifically for sponsoring employers, saving you from applying to positions where sponsorship is off the table before the first conversation even starts.
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Get Access To All JobsFrequently Asked Questions
Does a Senior Physical Design Engineer role qualify for H-1B sponsorship?
Yes. Physical design engineering is a textbook specialty occupation under USCIS criteria. The role requires at least a bachelor's degree in electrical engineering, computer engineering, or VLSI design, and the work involves highly specialized tasks like floorplanning, place-and-route, and timing closure at advanced process nodes. USCIS approval rates for engineering petitions with clear degree-to-job alignment are consistently high.
What degree do I need for an employer to sponsor my H-1B in this role?
A bachelor's degree or higher in electrical engineering, computer engineering, or a closely related field is the baseline. USCIS scrutinizes the match between your degree field and the specific duties of the role. A master's degree in VLSI or integrated circuit design is particularly strong. If your degree is in a broader field like general computer science, the employer's petition may need additional documentation to establish specialty occupation status.
Which employers hire Senior Physical Design Engineers with H-1B sponsorship?
Qualcomm, NVIDIA, Intel, Apple, Broadcom, AMD, Marvell, and MediaTek are among the largest sponsors for physical design roles based on DOL LCA disclosure data. Fabless semiconductor startups also sponsor regularly, though their H-1B processes are less established. Browse Migrate Mate to filter specifically for physical design roles at employers who are actively sponsoring work visas right now.
Can I get sponsored for an E-3 or TN visa as a Physical Design Engineer instead of H-1B?
Australian citizens can pursue E-3 sponsorship for this role, which has no lottery and a separate annual allocation of 10,500 visas that has never been fully used. Canadian and Mexican citizens may qualify for TN status under the engineer category, provided their degree is in an engineering field and the job duties align. Both are valid H-1B alternatives worth exploring if you hold the relevant citizenship.
How does the H-1B lottery affect sponsorship timelines for this role?
If you need a new H-1B and are subject to the annual cap, registration opens in March and selection is random. For fiscal year 2025, the selection rate was roughly 25%. If selected, your H-1B start date is October 1. Employers can file with premium processing to get a decision within 15 business days of USCIS receipt, which reduces uncertainty after selection but cannot accelerate the lottery itself.
What is the prevailing wage requirement for sponsored Senior Physical Design Engineer jobs?
U.S. employers sponsoring a visa must pay at least the prevailing wage, which is what workers in the same role, area, and experience level typically earn. The Department of Labor sets this rate to make sure companies aren't hiring foreign workers simply because they'd accept lower pay than a U.S. worker. It varies by job title, location, and experience. You can look up current prevailing wage rates for any occupation and location using the OFLC Wage Search page.
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