Mid Level ASIC Engineer Jobs
Mid level asic engineer jobs go to engineers ready to own blocks and subsystems end to end, make micro-architecture decisions with limited oversight, and guide junior teammates on RTL methodology and verification closure. Openings run across Electronics & Hardware, Technology & Software, and Aerospace & Defense, with employers like Cisco, NVIDIA, and SpaceX hiring at this level now.
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SUMMARY
At Apple, phenomenal ideas have a way of becoming great products and customer experiences very quickly. The industry is accustomed to Apple taping out the SOC’s for our various products at a rigorous pace. In order to achieve this, Apple’s best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high transparency and critically important role and requires close working relationships with many groups and an organized approach to coordinate all tasks in parallel to hit schedules consistently with a quality design. Our position requires knowledge of interconnect fabrics and system memory hierarchy.
DESCRIPTION
- Design & Integration of coherent and non-coherent fabrics into a subsystem or SoC with good understanding of on-chip interconnect architectures (NoC topologies, crossbars, arbitration).
- Own all aspects of RTL development design, templating, scripting and RTL generation.
- Work and collaborate with other designers in the group to deliver results.
- Integrate common/shared IP blocks to design and optimize memories/hard macros required for the block.
- Work with front-end synthesis/STA teams to ensure timing for the block is met.
- Work with power/performance and functional verification team to ensure high quality of the block.
- Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process.
MINIMUM QUALIFICATIONS
- Minimum of BS + 3 years relevant industry experience.
PREFERRED QUALIFICATIONS
- Knowledge of cache coherency protocols (MESI, MOESI, directory-based coherence) and memory hierarchy.
- A consistent track record of delivering large, sophisticated designs in high volume production for low power applications.
- Solid working experience with synthesis, power, performance and verification teams to develop and deliver high quality RTL design on time.
- Strong interpersonal skills, as the candidate will work with diverse groups within the company.
- Self-starter, highly motivated, highly organized, and schedule driven.
- Familiarity with all front-end tools including lint, CDC, synthesis.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
Apple accepts applications to this posting on an ongoing basis.
SUMMARY
At Apple, phenomenal ideas have a way of becoming great products and customer experiences very quickly. The industry is accustomed to Apple taping out the SOC’s for our various products at a rigorous pace. In order to achieve this, Apple’s best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high transparency and critically important role and requires close working relationships with many groups and an organized approach to coordinate all tasks in parallel to hit schedules consistently with a quality design. Our position requires knowledge of interconnect fabrics and system memory hierarchy.
DESCRIPTION
- Design & Integration of coherent and non-coherent fabrics into a subsystem or SoC with good understanding of on-chip interconnect architectures (NoC topologies, crossbars, arbitration).
- Own all aspects of RTL development design, templating, scripting and RTL generation.
- Work and collaborate with other designers in the group to deliver results.
- Integrate common/shared IP blocks to design and optimize memories/hard macros required for the block.
- Work with front-end synthesis/STA teams to ensure timing for the block is met.
- Work with power/performance and functional verification team to ensure high quality of the block.
- Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process.
MINIMUM QUALIFICATIONS
- Minimum of BS + 3 years relevant industry experience.
PREFERRED QUALIFICATIONS
- Knowledge of cache coherency protocols (MESI, MOESI, directory-based coherence) and memory hierarchy.
- A consistent track record of delivering large, sophisticated designs in high volume production for low power applications.
- Solid working experience with synthesis, power, performance and verification teams to develop and deliver high quality RTL design on time.
- Strong interpersonal skills, as the candidate will work with diverse groups within the company.
- Self-starter, highly motivated, highly organized, and schedule driven.
- Familiarity with all front-end tools including lint, CDC, synthesis.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
Apple accepts applications to this posting on an ongoing basis.
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Mid Level ASIC Engineer Jobs: Frequently Asked Questions
How do I get a mid level asic engineer job?
Position your experience around ownership, not just contribution. Highlight tapeouts you drove from RTL through sign-off, verification closures you led, or timing constraints you resolved independently. Recruiters at this level want to see that you shaped outcomes, not just executed tasks. Tailor your resume to show block-level responsibility and name the tools and methodologies you used without handholding.
Which companies hire mid level asic engineers?
Companies hiring mid level asic engineers right now include Cisco, NVIDIA, and SpaceX, based on current listings on Migrate Mate as of November 2026. Hiring at this level comes from semiconductor and fabless chip companies as well as large technology firms building custom silicon for compute, networking, and consumer applications.
Are there remote mid level asic engineer jobs?
Yes, though hardware-adjacent roles tend to skew more on-site than pure software positions. About 45% of mid level asic engineer openings are remote or hybrid as of November 2026, concentrated mostly at companies where verification, design, or physical implementation work can be done without lab access. Filtering by work setting on Migrate Mate will show you what is available.
How do I move up to a mid level asic engineer role?
The move from entry level to mid level in ASIC engineering comes from accumulating block ownership over time. Early in your career you contribute to subsystems under guidance. Mid level readiness shows when you can own RTL design or verification for a full block, debug complex failures independently, and communicate trade-offs to senior engineers. Demonstrable tapeout experience and familiarity with physical design constraints accelerate that progression significantly.
Which industries hire the most mid level asic engineers?
Mid Level asic engineer roles concentrate in Electronics & Hardware, Technology & Software, and Aerospace & Defense, based on current listings on Migrate Mate as of November 2026. These sectors drive demand because they build proprietary silicon at scale, requiring engineers with enough depth to own design blocks without constant supervision across the full RTL-to-GDSII flow.