Senior Level ASIC Physical Design Engineer Jobs
Senior level asic physical design engineer jobs put experienced engineers in charge of full-chip physical implementation, floor planning ownership, and the cross-functional teams that drive tapeout from RTL through signoff. Most openings are on-site or hybrid at companies across Technology & Software and Electronics & Hardware, with employers like Apple, Hewlett Packard Enterprise | HPE, and Cisco hiring at this level now.
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Showing 5 of 7+ Senior Level ASIC Physical Design Engineer jobs
Date posted 11/01/2026
Category Engineering
Hire Type Employee
Job ID 18710
Base Salary Range $180800-$271200
Remote Eligible No
Date Posted 11/01/2026
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are:
An experienced and visionary ASIC Digital Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in design methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of protocols such as DDR, PCIe/CXL, UCIe, AMBA and its applications. You can define and execute a new architecture for protocols such as UAL (Universal Accelerator Link). You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects.
What You’ll Be Doing:
- Defining and developing ASIC RTL design and verification at both chip and block levels.
- Creating and executing design plans for complex digital designs, particularly focusing on DDR, PCIe, CXL, UAL, UCIe IO protocols.
- Collaborating with cross-functional teams to ensure seamless integration and functionality of designs.
- Utilizing advanced design and verification methodologies and tools to achieve high-quality results.
- Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement.
- Communicating with internal and external stakeholders to align on project goals and deliverables.
The Impact You Will Have:
- Enhancing the reliability and performance of Synopsys’ digital design processes.
- Driving innovations in DDR, PCIe, UAL, UCIe technology, contributing to the development of cutting-edge semiconductor solutions.
- Improving time-to-market for high-performance silicon chips through efficient methodologies.
- Building and nurturing a highly skilled development team, elevating overall project quality.
- Influencing strategic decisions that shape the future of Synopsys’ capabilities.
- Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements.
What You’ll Need:
- BSEE or BSCE +12 years or an advanced degree and +10 years industry experience
- Extensive experience in ASIC RTL design.
- In-depth knowledge of DDR, PCIe, UAL, UCIe and similar IO protocols and their applications.
- Proficiency in advanced digital design tools and methodologies.
- Strong problem-solving skills and the ability to work independently.
- Excellent communication skills for effective collaboration with diverse teams.
Who You Are:
- A visionary leader with a strategic mindset.
- A mentor who fosters talent and encourages innovation.
- A proactive problem solver who thrives in complex environments.
- An effective communicator with the ability to convey technical concepts to a broad audience.
- A team player who values collaboration and diversity.
The Team You’ll Be A Part Of:
You will join a dynamic and innovative team focused on advancing Synopsys' design technologies. Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry. Specifically, according to a match profile, you will be a key technical contributor to the architecture and execution of one of DDR/PCIe/UAL/UCIe digital core protocols.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can
Date posted 11/01/2026
Category Engineering
Hire Type Employee
Job ID 18710
Base Salary Range $180800-$271200
Remote Eligible No
Date Posted 11/01/2026
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are:
An experienced and visionary ASIC Digital Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in design methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of protocols such as DDR, PCIe/CXL, UCIe, AMBA and its applications. You can define and execute a new architecture for protocols such as UAL (Universal Accelerator Link). You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects.
What You’ll Be Doing:
- Defining and developing ASIC RTL design and verification at both chip and block levels.
- Creating and executing design plans for complex digital designs, particularly focusing on DDR, PCIe, CXL, UAL, UCIe IO protocols.
- Collaborating with cross-functional teams to ensure seamless integration and functionality of designs.
- Utilizing advanced design and verification methodologies and tools to achieve high-quality results.
- Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement.
- Communicating with internal and external stakeholders to align on project goals and deliverables.
The Impact You Will Have:
- Enhancing the reliability and performance of Synopsys’ digital design processes.
- Driving innovations in DDR, PCIe, UAL, UCIe technology, contributing to the development of cutting-edge semiconductor solutions.
- Improving time-to-market for high-performance silicon chips through efficient methodologies.
- Building and nurturing a highly skilled development team, elevating overall project quality.
- Influencing strategic decisions that shape the future of Synopsys’ capabilities.
- Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements.
What You’ll Need:
- BSEE or BSCE +12 years or an advanced degree and +10 years industry experience
- Extensive experience in ASIC RTL design.
- In-depth knowledge of DDR, PCIe, UAL, UCIe and similar IO protocols and their applications.
- Proficiency in advanced digital design tools and methodologies.
- Strong problem-solving skills and the ability to work independently.
- Excellent communication skills for effective collaboration with diverse teams.
Who You Are:
- A visionary leader with a strategic mindset.
- A mentor who fosters talent and encourages innovation.
- A proactive problem solver who thrives in complex environments.
- An effective communicator with the ability to convey technical concepts to a broad audience.
- A team player who values collaboration and diversity.
The Team You’ll Be A Part Of:
You will join a dynamic and innovative team focused on advancing Synopsys' design technologies. Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry. Specifically, according to a match profile, you will be a key technical contributor to the architecture and execution of one of DDR/PCIe/UAL/UCIe digital core protocols.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can
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Senior Level ASIC Physical Design Engineer Jobs: Frequently Asked Questions
How do I get a senior level asic physical design engineer job?
Employers at this level expect ownership of complex physical design flows, not just task execution. Candidates who stand out demonstrate end-to-end tapeout experience across advanced nodes, proficiency with industry-standard EDA tools, and the ability to define methodology and mentor junior engineers. A portfolio of shipped silicon with documented contributions to timing closure, power delivery, or floorplan strategy is a stronger signal than years alone.
Which companies hire senior level asic physical design engineers?
Companies hiring senior level asic physical design engineers right now include Apple, Hewlett Packard Enterprise | HPE, and Cisco, based on current listings on Migrate Mate as of November 2026. Hiring at this level is led by semiconductor fabless companies, vertically integrated tech firms building custom silicon, and defense and aerospace contractors developing specialized ASICs.
Are there remote senior level asic physical design engineer jobs?
Yes, though physical design roles skew more on-site than many engineering disciplines due to lab access and EDA tool licensing requirements. About 20% of senior level asic physical design engineer openings are remote or hybrid as of November 2026, with hybrid arrangements more common than fully remote at this seniority level.
What makes a asic physical design engineer role senior level?
Senior level roles are defined by scope and accountability rather than task complexity alone. A senior asic physical design engineer owns a full block or subsystem from floorplan through tapeout signoff, sets physical design guidelines for the team, resolves critical path and DRC closure challenges independently, and mentors more junior engineers. Influencing tool selection, flow development, and cross-team methodology decisions is expected at this stage.
Which industries hire the most senior level asic physical design engineers?
Senior Level asic physical design engineer roles concentrate in Technology & Software and Electronics & Hardware, based on current listings on Migrate Mate as of November 2026. These sectors drive hiring because they are actively developing custom silicon for high-performance computing, networking, AI acceleration, and defense applications where in-house physical design expertise at a senior level is a competitive necessity.