Asic Verification Engineer Jobs in California
Asic verification engineer jobs in California represent one of the most active and competitive markets in the country, concentrated in semiconductor and fabless chip design, consumer electronics, and automotive silicon, with openings at every level from junior verification engineer through principal and staff engineer. The largest hiring clusters are in San Jose, San Diego, and Santa Clara, where companies like Qualcomm, Apple, and Intel maintain substantial design and verification teams. Functional coverage verification, UVM methodology, and formal verification are the most consistently in-demand specialties across California listings. Find a role that fits below and apply directly.
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Showing 5 of 53+ Asic Verification Engineer jobs
K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.
The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.
With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.
The Role
We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon.
Responsibilities
- Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
- Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
- Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
- Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
- Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
- Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
- Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
- Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
- Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
- Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
- Participate in ASIC team interviews.
- Drive advancement of DV methodologies and improvements.
- Manage external IP providers and verification partners when needed.
- Take lead on large and/or complex systems.
Qualifications
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
- 10+ years of experience in ASIC/SoC verification.
- Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
- Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
- Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
- Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
- Experience with developing and integrating reference models.
- Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
- Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
- Involvement in post-silicon validation planning and execution.
Nice to Have
- Experience with low power verification.
- Experience with analog behavioral models.
- Familiarity with physical design flows.
- Experience working in cross-functional, geographically distributed teams.
- Experience in space, telecom, or RF/digital mixed systems is a plus.
Compensation and Benefits:
- Base salary range for this role is $190,000 – $285,000 + equity in the company
- Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
- Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!
If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.
Export Compliance
As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."
The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
Equal Opportunity
K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.
The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.
With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.
The Role
We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon.
Responsibilities
- Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
- Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
- Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
- Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
- Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
- Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
- Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
- Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
- Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
- Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
- Participate in ASIC team interviews.
- Drive advancement of DV methodologies and improvements.
- Manage external IP providers and verification partners when needed.
- Take lead on large and/or complex systems.
Qualifications
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
- 10+ years of experience in ASIC/SoC verification.
- Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
- Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
- Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
- Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
- Experience with developing and integrating reference models.
- Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
- Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
- Involvement in post-silicon validation planning and execution.
Nice to Have
- Experience with low power verification.
- Experience with analog behavioral models.
- Familiarity with physical design flows.
- Experience working in cross-functional, geographically distributed teams.
- Experience in space, telecom, or RF/digital mixed systems is a plus.
Compensation and Benefits:
- Base salary range for this role is $190,000 – $285,000 + equity in the company
- Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
- Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!
If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.
Export Compliance
As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."
The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
Equal Opportunity
K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
See All 53 Asic Verification Engineer Jobs in California
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Find JobsAsic Verification Engineer Jobs by City in California
Where California roles are concentrated, by current openings.
Asic Verification Engineer Job Market in California
A snapshot from current California openings, updated as new roles post.
Who's Hiring
Top Industries Hiring
- Technology & Software
- Electronics & Hardware
- Telecommunications
- Artificial Intelligence
What California Employers Look For
The qualifications that appear most often in asic verification engineer jobs across California.
- Bachelor's or master's degree in electrical engineering, computer engineering, or computer science
- Proficiency in SystemVerilog and UVM-based testbench development for block and chip-level verification
- Experience with functional coverage closure and constrained-random verification methodology
- Familiarity with simulation tools such as VCS, Xcelium, or Questa in a Linux environment
- Ability to write and debug RTL assertions using SVA for formal or dynamic verification
- Experience with scripting languages such as Python or Perl for test automation and regression management
Asic Verification Engineer Jobs in California: Frequently Asked Questions
How do you become a asic verification engineer in California?
Asic verification engineering in California does not require a state-issued license, so the path runs through education and demonstrated technical skills. Most California employers expect at least a bachelor's degree in electrical engineering, computer engineering, or a closely related field, with a master's degree increasingly preferred for roles in advanced nodes. Building hands-on experience with SystemVerilog, UVM, and industry simulation tools through coursework, internships, or open-source projects is the most direct way to enter California's semiconductor hiring pipeline.
How much do asic verification engineers make in California?
Asic verification engineers in California earn a median of about $160,520 a year, based on May 2025 Bureau of Labor Statistics wage data, ranging from around $97,140 for the lowest 10% to over $225,400 for the top 10%. Pay rises with experience, specialty, and employer.
Which companies hire asic verification engineers in California?
Employers hiring asic verification engineers in California right now include Google, NVIDIA, and Meta, based on current listings on Migrate Mate as of November 2026. California's dense concentration of fabless semiconductor companies, consumer electronics OEMs, and automotive chip developers means demand is spread across both large established names and well-funded design startups, particularly in the San Jose and San Diego corridors.
Which California cities have the most asic verification engineer jobs?
Sunnyvale, San Jose, and Santa Clara have the most asic verification engineer openings in California. The Silicon Valley corridor anchors demand through its dense cluster of fabless chip companies, EDA vendors, and consumer electronics headquarters, while San Diego draws significant hiring from Qualcomm's large local presence and a growing automotive and 5G silicon ecosystem.
Are there remote asic verification engineer jobs in California?
Yes, but they're less common than in purely software-focused roles, since ASIC verification regularly requires access to internal simulation infrastructure, licensed EDA toolchains, and lab hardware. About 52% of asic verification engineer openings tied to California are remote or hybrid as of November 2026, with hybrid arrangements more prevalent than fully remote. Tasks most amenable to remote work include testbench development, scripting, and coverage analysis rather than bringup and debug work.
How can I get hired as a asic verification engineer in California with little or no experience?
The most realistic entry path is a master's program at a California engineering school, such as UC San Diego, UC Santa Cruz, or San Jose State, where curriculum projects and industry-linked labs provide the SystemVerilog and UVM exposure California employers expect. Large California semiconductor companies including Qualcomm and Broadcom run structured internship and new-graduate rotational programs that regularly convert to full-time verification roles. Candidates who build a public portfolio demonstrating functional coverage closure or a complete UVM environment on an open-source core significantly improve their standing against more experienced applicants.
Where can I find and apply to asic verification engineer jobs in California?
You can find and apply to asic verification engineer jobs in California on Migrate Mate, which lists current California openings updated in real time. Search the listings below to see roles that match your experience level and location preference, then apply directly to the ones that fit.
See All 53 Asic Verification Engineer Jobs in California
Find roles in California that match your experience and apply in just a few clicks.
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