Asic Verification Engineer Jobs
Asic Verification Engineer jobs are open across semiconductor, consumer electronics, automotive, and defense industries, at every level from new-grad to staff and principal, with specializations in UVM, formal verification, and emulation. Find a role that fits from the openings below and apply directly.
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Showing 5 of 65+ Asic Verification Engineer jobs
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Sunnyvale, CA, USA; Tel Aviv, Israel; Haifa, Israel.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 8 years of experience in design verification (DV) with a focus on digital signal processing (DSP), communication systems, or arithmetic logic blocks.
- Experience with scripting in Python, Perl, or Makefile for automation.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
- Experience with Mixed-Signal verification techniques such as Real Number Modeling (RNM, SystemVerilog-Wreal) or SystemVerilog-AMS.
- Functional knowledge of adaptive equalization architectures (FFE/DFE) and timing recovery loops.
- Programming proficiency in Python, MATLAB, or C/C++ for testbench automation and reference modeling.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will define and execute the verification strategy for high-speed Physical Layer (PHY) digital blocks. This role focuses on the functional and mathematical verification of complex DSP algorithms, digital-analog boundaries, and signal processing logic. This position requires a strong technical foundation in communication theory, fixed-point arithmetic, and mixed-signal co-simulation.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Verify RTL implementations against high-level architectural reference models (MATLAB, C++, or SystemC) using bit-exact and fixed-point verification methodologies.
- Verify the stability, tracking capability, and convergence of adaptive equalization loops (FFE, DFE) and timing recovery systems under varying channel impairments.
- Model and verify the functional interface between Digital DSP blocks and the Analog Front End (AFE) using Real Number Modeling (RNM) or SystemVerilog-AMS.
- Design, implement, and maintain scalable UVM-based simulation environments, SystemVerilog Assertions (SVA), and functional coverage metrics for digital signal processing blocks.
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Sunnyvale, CA, USA; Tel Aviv, Israel; Haifa, Israel.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 8 years of experience in design verification (DV) with a focus on digital signal processing (DSP), communication systems, or arithmetic logic blocks.
- Experience with scripting in Python, Perl, or Makefile for automation.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
- Experience with Mixed-Signal verification techniques such as Real Number Modeling (RNM, SystemVerilog-Wreal) or SystemVerilog-AMS.
- Functional knowledge of adaptive equalization architectures (FFE/DFE) and timing recovery loops.
- Programming proficiency in Python, MATLAB, or C/C++ for testbench automation and reference modeling.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will define and execute the verification strategy for high-speed Physical Layer (PHY) digital blocks. This role focuses on the functional and mathematical verification of complex DSP algorithms, digital-analog boundaries, and signal processing logic. This position requires a strong technical foundation in communication theory, fixed-point arithmetic, and mixed-signal co-simulation.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Verify RTL implementations against high-level architectural reference models (MATLAB, C++, or SystemC) using bit-exact and fixed-point verification methodologies.
- Verify the stability, tracking capability, and convergence of adaptive equalization loops (FFE, DFE) and timing recovery systems under varying channel impairments.
- Model and verify the functional interface between Digital DSP blocks and the Analog Front End (AFE) using Real Number Modeling (RNM) or SystemVerilog-AMS.
- Design, implement, and maintain scalable UVM-based simulation environments, SystemVerilog Assertions (SVA), and functional coverage metrics for digital signal processing blocks.
Asic Verification Engineer Jobs by Experience Level
See All 65 Asic Verification Engineer Jobs
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Find JobsAsic Verification Engineer Job Market
Who's Hiring
- Google11
- NVIDIA9
- Meta7
- Nokia3
- Qualcomm3
Top Industries Hiring
- Technology & Software13
- Electronics & Hardware8
- Telecommunications4
- Artificial Intelligence3
- Retail1
What Employers Look For
The qualifications that appear most often in asic verification engineer jobs.
- Proficiency in SystemVerilog and UVM for constrained-random testbench development
- Experience with industry-standard simulators such as VCS, Xcelium, or Questasim
- Familiarity with functional coverage, code coverage, and closure-driven verification planning
- Knowledge of formal verification tools including JasperGold or Synopsys VC Formal
- Bachelor's or master's degree in electrical engineering, computer engineering, or a related field
- Ability to read and interpret RTL written in Verilog or VHDL for debug and testbench alignment
Tips for Your Asic Verification Engineer Job Search
Tailor your resume to verification methodology
Hiring managers scan for UVM, SystemVerilog, and coverage-driven verification upfront. List the specific methodologies you've used for each role, not just the simulators. Vague claims like 'verification experience' get passed over when engineers with explicit UVM scoreboards and functional coverage metrics are applying.
Apply early to roles that fit
Migrate Mate lists asic verification engineer openings from across the United States in one place, so you can find roles that match and apply directly to each listing.
Filter openings by design domain
Verification roles differ sharply between CPU, memory, mixed-signal, and connectivity blocks. When searching, target postings that match the design domain you've actually worked in. Applying with directly relevant block-level or subsystem experience dramatically improves your callback rate.
Document your coverage closure contributions
Resumes that quantify coverage closure, such as the percentage of functional coverage bins you closed or bugs you found in formal versus simulation, stand out. Reviewers want to see that you drove verification completeness, not just wrote tests and waited for results.
Prepare a testbench walkthrough for interviews
Technical screens almost always include a live walkthrough of a UVM testbench or constrained-random environment you built. Practice explaining your scoreboard architecture, sequence layering, and how you handled corner-case generation out loud before the interview, not just in your head.
Negotiate using competing offer timelines
Semiconductor hiring moves slowly, so if you have multiple applications in flight, let recruiters know when you have a deadline from another offer. Teams with open headcount often accelerate approval to avoid losing a candidate, especially at senior and staff levels where the bench is thin.
Asic Verification Engineer Jobs: Frequently Asked Questions
Which companies are hiring the most asic verification engineers?
The companies hiring the most asic verification engineers right now include Google, NVIDIA, and Meta, with the largest share of openings in California, Texas, and Washington, based on current listings on Migrate Mate as of September 2026. Demand is concentrated at semiconductor design houses, chipset divisions of large technology companies, and automotive-grade silicon teams.
How many asic verification engineer jobs are remote?
About 40% of asic verification engineer openings are fully remote or hybrid as of September 2026, reflecting an industry where much of the verification workflow is tool-based and cloud-accessible. Sub-areas such as formal verification and testbench development tend to have higher remote availability than roles tied to lab hardware, emulation platforms, or pre-silicon bring-up work.
How do you become a asic verification engineer?
Start by building a foundation in digital logic design and hardware description languages, then focus on SystemVerilog and the UVM methodology through coursework or personal projects. Contribute to open-source verification environments or complete an internship that gives you real testbench ownership. Employers look for demonstrated experience closing coverage on a real or academic block, so document that work clearly before applying.
How do you get hired as a asic verification engineer with little experience?
Focus on building a small but complete UVM testbench for a public-domain RTL block, such as a UART or SPI controller, and publish it with coverage reports. Internships at semiconductor companies are the most direct path, and university research positions working on CPU or accelerator verification provide the same credibility. Targeting companies with structured new-grad verification rotations also gives you entry without requiring prior industry tapeout experience.
What does the asic verification engineer interview process look like?
The process typically starts with a recruiter screen focused on your methodology background, followed by a technical phone interview covering SystemVerilog syntax, OOP concepts in UVM, and coverage models. Later rounds usually include a take-home or live coding exercise building a scoreboard or sequence, plus a system design discussion where you walk through a verification plan for a given block. Final rounds often involve a panel with the verification lead and a design engineer.
Where can I find and apply to asic verification engineer jobs?
You can find and apply to asic verification engineer jobs on Migrate Mate, which lists current openings from across the United States. Search the listings to find roles that match your methodology background, design domain experience, and seniority level, then apply directly to each one that fits.
See All 65 Asic Verification Engineer Jobs
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