Asic Verification Engineer Jobs
Asic Verification Engineer jobs are open across semiconductor, consumer electronics, automotive, and defense industries, at every level from new-grad to staff and principal, with specializations in UVM, formal verification, and emulation. Find a role that fits from the openings below and apply directly.
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Senior ASIC Design Verification Engineer - Slingshot
This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office.
Who We Are:
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.
Job Description:
About the Team and the Project
Our team develops HPE Slingshot, an industry-leading interconnect used in some of the world's largest HPC and AI systems. As a Senior Design Verification Engineer, you will work alongside experienced architects, logic designers, and verification engineers on the switch and NIC ASICs for a future generation of Slingshot. You will own significant verification scope, set technical direction for a block or subsystem, and help shape how our team applies emerging agentic AI workflows to solve complex engineering problems.
In this role you will be responsible for all phases of pre-silicon design verification, including design verification methodology, test-plan development, testbench development, coverage closure, and sign-off reviews.
Responsibilities
- Follow and help define the team's design verification methodology.
- Develop SystemVerilog and UVM testbench components, including bus functional models that drive and monitor stimulus.
- Plan and implement block and integration level scoreboards and checkers to verify functional behavior.
- Write and analyze functional coverage, providing input to block level milestones.
- Triage regression failures and identify logic bugs, while driving bug closure.
- Apply scripting, automation, and AI-assisted and agentic tools to improve the speed and quality of the verification process.
- Provide guidance and mentoring to less experienced staff members to set an example of VLSI design and development innovation and excellence.
- Participate in and provide input on the process for selection of future technical leaders.
- Drive VLSI innovation and integration of new technologies into projects and activities in the design organization.
Education and Experience Required
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
- 10+ years of experience in VLSI design, verification, or implementation.
Knowledge and Skills
- Expert level knowledge of SystemVerilog and of OVM or UVM methodologies.
- Expert level knowledge of programming and scripting languages, hardware description languages, electronic design automation (EDA), and/or FPGA tools.
- Expert level analytical and problem solving skills.
- Ability to excel in a distributed team environment.
- Executive level written and verbal communication skills; mastery in English.
Preferred Skills
- Experience verifying high-speed networking, switching, or NIC ASICs.
- Experience with agentic AI coding tools and workflows applied to verification.
- Experience with Python, Perl, Tcl, or another scripting language in Linux development environments.
- Experience working as part of a geographically distributed team.
Accessibility
HPE is committed to creating an inclusive and accessible workplace and encourages applications from all qualified individuals, including those with disabilities. If you believe you require accommodation during any stage of the application or interview process, please submit your request by completing our secure form linked here.
Note: This option is reserved for applicants needing assistance/reasonable accommodation related to a disability.
What We Can Offer You:
Health & Wellbeing
We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
Personal & Professional Development
We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.
Unconditional Inclusion
We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.
Job:
Engineering
Job Level:
TCP_04
The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
- United States of America: Annual Salary USD 147,000 - 279,000 in Colorado // 140,000 - 321,000 in Minnesota & Wisconsin
The listed salary range reflects base salary. Variable incentives may also be offered.
Information about employee benefits offered in the US can be found at myhperewards.com/main/new-hire-enrollment.html
The estimated job application period closure is February 1 2027; this timeline is provided for transparency and internal planning purposes.
HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together.
Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.
HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.
Recruitment Fraud Alert
We have become aware of an increase in fraudulent recruitment activities in which individuals impersonate our company or authorized recruitment agencies to offer fake employment opportunities. These scams may occur through false websites, emails, social media, or chat-based applications and often aim to obtain personal information or money. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We also never request personal information such as back account details, Social Security numbers, or national IDs via social media or chat applications.
All legitimate job opportunities will come through official company channels, and candidates are responsible for verifying the credentials of any third party claiming to represent the company. Any reliance on fraudulent communication is at the individual’s own risk, and HPE disclaims legal liability for any resulting damages. If you suspect recruitment fraud, do not share personal information or make any payments and report the incident to your local authorities immediately.
Senior ASIC Design Verification Engineer - Slingshot
This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office.
Who We Are:
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.
Job Description:
About the Team and the Project
Our team develops HPE Slingshot, an industry-leading interconnect used in some of the world's largest HPC and AI systems. As a Senior Design Verification Engineer, you will work alongside experienced architects, logic designers, and verification engineers on the switch and NIC ASICs for a future generation of Slingshot. You will own significant verification scope, set technical direction for a block or subsystem, and help shape how our team applies emerging agentic AI workflows to solve complex engineering problems.
In this role you will be responsible for all phases of pre-silicon design verification, including design verification methodology, test-plan development, testbench development, coverage closure, and sign-off reviews.
Responsibilities
- Follow and help define the team's design verification methodology.
- Develop SystemVerilog and UVM testbench components, including bus functional models that drive and monitor stimulus.
- Plan and implement block and integration level scoreboards and checkers to verify functional behavior.
- Write and analyze functional coverage, providing input to block level milestones.
- Triage regression failures and identify logic bugs, while driving bug closure.
- Apply scripting, automation, and AI-assisted and agentic tools to improve the speed and quality of the verification process.
- Provide guidance and mentoring to less experienced staff members to set an example of VLSI design and development innovation and excellence.
- Participate in and provide input on the process for selection of future technical leaders.
- Drive VLSI innovation and integration of new technologies into projects and activities in the design organization.
Education and Experience Required
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
- 10+ years of experience in VLSI design, verification, or implementation.
Knowledge and Skills
- Expert level knowledge of SystemVerilog and of OVM or UVM methodologies.
- Expert level knowledge of programming and scripting languages, hardware description languages, electronic design automation (EDA), and/or FPGA tools.
- Expert level analytical and problem solving skills.
- Ability to excel in a distributed team environment.
- Executive level written and verbal communication skills; mastery in English.
Preferred Skills
- Experience verifying high-speed networking, switching, or NIC ASICs.
- Experience with agentic AI coding tools and workflows applied to verification.
- Experience with Python, Perl, Tcl, or another scripting language in Linux development environments.
- Experience working as part of a geographically distributed team.
Accessibility
HPE is committed to creating an inclusive and accessible workplace and encourages applications from all qualified individuals, including those with disabilities. If you believe you require accommodation during any stage of the application or interview process, please submit your request by completing our secure form linked here.
Note: This option is reserved for applicants needing assistance/reasonable accommodation related to a disability.
What We Can Offer You:
Health & Wellbeing
We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
Personal & Professional Development
We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.
Unconditional Inclusion
We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.
Job:
Engineering
Job Level:
TCP_04
The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
- United States of America: Annual Salary USD 147,000 - 279,000 in Colorado // 140,000 - 321,000 in Minnesota & Wisconsin
The listed salary range reflects base salary. Variable incentives may also be offered.
Information about employee benefits offered in the US can be found at myhperewards.com/main/new-hire-enrollment.html
The estimated job application period closure is February 1 2027; this timeline is provided for transparency and internal planning purposes.
HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together.
Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.
HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.
Recruitment Fraud Alert
We have become aware of an increase in fraudulent recruitment activities in which individuals impersonate our company or authorized recruitment agencies to offer fake employment opportunities. These scams may occur through false websites, emails, social media, or chat-based applications and often aim to obtain personal information or money. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We also never request personal information such as back account details, Social Security numbers, or national IDs via social media or chat applications.
All legitimate job opportunities will come through official company channels, and candidates are responsible for verifying the credentials of any third party claiming to represent the company. Any reliance on fraudulent communication is at the individual’s own risk, and HPE disclaims legal liability for any resulting damages. If you suspect recruitment fraud, do not share personal information or make any payments and report the incident to your local authorities immediately.
Asic Verification Engineer Jobs by Experience Level
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Who's Hiring
Top Industries Hiring
- Technology & Software10
- Electronics & Hardware6
- Telecommunications5
- Artificial Intelligence2
- Staffing & Recruiting1
What Employers Look For
The qualifications that appear most often in asic verification engineer jobs.
- Proficiency in SystemVerilog and UVM for constrained-random testbench development
- Experience with industry-standard simulators such as VCS, Xcelium, or Questasim
- Familiarity with functional coverage, code coverage, and closure-driven verification planning
- Knowledge of formal verification tools including JasperGold or Synopsys VC Formal
- Bachelor's or master's degree in electrical engineering, computer engineering, or a related field
- Ability to read and interpret RTL written in Verilog or VHDL for debug and testbench alignment
Tips for Your Asic Verification Engineer Job Search
Tailor your resume to verification methodology
Hiring managers scan for UVM, SystemVerilog, and coverage-driven verification upfront. List the specific methodologies you've used for each role, not just the simulators. Vague claims like 'verification experience' get passed over when engineers with explicit UVM scoreboards and functional coverage metrics are applying.
Apply early to roles that fit
Migrate Mate lists asic verification engineer openings from across the United States in one place, so you can find roles that match and apply directly to each listing.
Filter openings by design domain
Verification roles differ sharply between CPU, memory, mixed-signal, and connectivity blocks. When searching, target postings that match the design domain you've actually worked in. Applying with directly relevant block-level or subsystem experience dramatically improves your callback rate.
Document your coverage closure contributions
Resumes that quantify coverage closure, such as the percentage of functional coverage bins you closed or bugs you found in formal versus simulation, stand out. Reviewers want to see that you drove verification completeness, not just wrote tests and waited for results.
Prepare a testbench walkthrough for interviews
Technical screens almost always include a live walkthrough of a UVM testbench or constrained-random environment you built. Practice explaining your scoreboard architecture, sequence layering, and how you handled corner-case generation out loud before the interview, not just in your head.
Negotiate using competing offer timelines
Semiconductor hiring moves slowly, so if you have multiple applications in flight, let recruiters know when you have a deadline from another offer. Teams with open headcount often accelerate approval to avoid losing a candidate, especially at senior and staff levels where the bench is thin.
Asic Verification Engineer Jobs: Frequently Asked Questions
Which companies are hiring the most asic verification engineers?
The companies hiring the most asic verification engineers right now include Meta, Hewlett Packard Enterprise | HPE, and Google, with the largest share of openings in California, Texas, and Washington, based on current listings on Migrate Mate as of November 2026. Demand is concentrated at semiconductor design houses, chipset divisions of large technology companies, and automotive-grade silicon teams.
How many asic verification engineer jobs are remote?
About 55% of asic verification engineer openings are fully remote or hybrid as of November 2026, reflecting an industry where much of the verification workflow is tool-based and cloud-accessible. Sub-areas such as formal verification and testbench development tend to have higher remote availability than roles tied to lab hardware, emulation platforms, or pre-silicon bring-up work.
How do you become a asic verification engineer?
Start by building a foundation in digital logic design and hardware description languages, then focus on SystemVerilog and the UVM methodology through coursework or personal projects. Contribute to open-source verification environments or complete an internship that gives you real testbench ownership. Employers look for demonstrated experience closing coverage on a real or academic block, so document that work clearly before applying.
How do you get hired as a asic verification engineer with little experience?
Focus on building a small but complete UVM testbench for a public-domain RTL block, such as a UART or SPI controller, and publish it with coverage reports. Internships at semiconductor companies are the most direct path, and university research positions working on CPU or accelerator verification provide the same credibility. Targeting companies with structured new-grad verification rotations also gives you entry without requiring prior industry tapeout experience.
What does the asic verification engineer interview process look like?
The process typically starts with a recruiter screen focused on your methodology background, followed by a technical phone interview covering SystemVerilog syntax, OOP concepts in UVM, and coverage models. Later rounds usually include a take-home or live coding exercise building a scoreboard or sequence, plus a system design discussion where you walk through a verification plan for a given block. Final rounds often involve a panel with the verification lead and a design engineer.
Where can I find and apply to asic verification engineer jobs?
You can find and apply to asic verification engineer jobs on Migrate Mate, which lists current openings from across the United States. Search the listings to find roles that match your methodology background, design domain experience, and seniority level, then apply directly to each one that fits.
See All 64 Asic Verification Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
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