Senior Devops Engineer Jobs at Microsoft with Visa Sponsorship
Senior Devops Engineer jobs at Microsoft sit at the intersection of cloud infrastructure, automation, and enterprise-scale reliability engineering. Microsoft has a strong track record of sponsoring international engineers across multiple visa categories for this function, making it a realistic target for skilled DevOps professionals seeking U.S. work authorization.
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Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.
The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the DFX (Design for Test & Debug) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Senior Design for Test (DFT) Engineer to join the team.
Responsibilities
- Own block level DFT u-arch specification documentation & provide Test solutions in design for test chips and products.
- Ensure DFX goals (testability, debug, manufacturability, System Test, System Debug, Repair) are met by these IPs, ensure analog to digital boundaries are reliably tested. Review coverage metrics for Digital logic.
- Maintain & enhance existing DFT tools by understanding product needs & tailor solutions for current and upcoming products, also with the use of AI.
- Provide test plans and engage closely with verification engineers to perform waveform reviews.
- Ensure RTL quality pre-DFT to ensure the RTL is good for DFT insertion and coverage.
- Hold a primary role in enabling silicon by working directly with test engineers to bring up test vectors, and analyzing yield & diagnosis.
- Work as part of DFX (Test & Debug) team & closely collaborate with highly energetic cross functional team members (Architects, front-end & back-end design/verification, Physical design, and post-silicon manufacturing) with respect and with One Microsoft mentality to establish synergies.
Qualifications
Required Qualifications:
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
- OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
- OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
- OR equivalent experience.
- 4+ years of experience in the field of DFT knowledge about industry standard practice in Design for Test
- ATPG, JTAG, Memory BIST, and trade-offs between test quality and test time
Other Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings:
- Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
Preferred Qualifications:
- Experience with Test Chip development and some unique challenges it brings about for DFT.
- Experience developing Scan architecture & micro-arch specifications as it relates to large SOCs along with scan insertion techniques for IP's like PLL’s, IO’s & Power circuits.
- Expert at Scan ATPG, Stuck-At, At-Speed insertion, boundary coverage, compression & retargeting flows - using EDA tools like Siemens Tessent or Synopsys TestMax.
- Knowledge of Verilog or System Verilog with experience using simulators and waveform debugging tools.
- Ability to pioneer flows for Gate-level simulation (GLS), perform coverage analysis, and debug for achieving high fault coverage.
- Experience with Static Timing Analysis & constraint generation.
- Experience with ATE and Silicon bring-up with proficiency in Mentor Tessent / Synopsys tools for Yield & Diagnosis.
- Proactive & self-motivated, eager to learn and contribute in a team environment, committed and accountable.
- Proficient in scripting languages (Tcl & Perl), and use of AI to improve work efficiency.
- Confident problem solver who thrives under pressure to find new, creative solutions.
SCHIE #CSME
Compensation
- The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process.
Overview
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.
The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the DFX (Design for Test & Debug) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Senior Design for Test (DFT) Engineer to join the team.
Responsibilities
- Own block level DFT u-arch specification documentation & provide Test solutions in design for test chips and products.
- Ensure DFX goals (testability, debug, manufacturability, System Test, System Debug, Repair) are met by these IPs, ensure analog to digital boundaries are reliably tested. Review coverage metrics for Digital logic.
- Maintain & enhance existing DFT tools by understanding product needs & tailor solutions for current and upcoming products, also with the use of AI.
- Provide test plans and engage closely with verification engineers to perform waveform reviews.
- Ensure RTL quality pre-DFT to ensure the RTL is good for DFT insertion and coverage.
- Hold a primary role in enabling silicon by working directly with test engineers to bring up test vectors, and analyzing yield & diagnosis.
- Work as part of DFX (Test & Debug) team & closely collaborate with highly energetic cross functional team members (Architects, front-end & back-end design/verification, Physical design, and post-silicon manufacturing) with respect and with One Microsoft mentality to establish synergies.
Qualifications
Required Qualifications:
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
- OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
- OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
- OR equivalent experience.
- 4+ years of experience in the field of DFT knowledge about industry standard practice in Design for Test
- ATPG, JTAG, Memory BIST, and trade-offs between test quality and test time
Other Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings:
- Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
Preferred Qualifications:
- Experience with Test Chip development and some unique challenges it brings about for DFT.
- Experience developing Scan architecture & micro-arch specifications as it relates to large SOCs along with scan insertion techniques for IP's like PLL’s, IO’s & Power circuits.
- Expert at Scan ATPG, Stuck-At, At-Speed insertion, boundary coverage, compression & retargeting flows - using EDA tools like Siemens Tessent or Synopsys TestMax.
- Knowledge of Verilog or System Verilog with experience using simulators and waveform debugging tools.
- Ability to pioneer flows for Gate-level simulation (GLS), perform coverage analysis, and debug for achieving high fault coverage.
- Experience with Static Timing Analysis & constraint generation.
- Experience with ATE and Silicon bring-up with proficiency in Mentor Tessent / Synopsys tools for Yield & Diagnosis.
- Proactive & self-motivated, eager to learn and contribute in a team environment, committed and accountable.
- Proficient in scripting languages (Tcl & Perl), and use of AI to improve work efficiency.
- Confident problem solver who thrives under pressure to find new, creative solutions.
SCHIE #CSME
Compensation
- The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process.
See all 44+ Senior Devops Engineer Jobs at Microsoft
Sign up for free to unlock all listings, filter by visa type, and get alerts for new Senior Devops Engineer Jobs at Microsoft.
Get Access To All JobsTips for Finding Senior Devops Engineer Jobs at Microsoft
Align your credentials to Microsoft's engineering levels
Microsoft maps DevOps roles to internal engineering levels. Before applying, review the seniority signals in job postings closely. Your resume should reflect scope of ownership, not just tooling familiarity, to clear the initial leveling screen.
Target teams running Azure-native infrastructure stacks
Microsoft's DevOps hiring concentrates heavily in teams building on Azure, GitHub Actions, and Kubernetes at scale. Framing your experience around those specific platforms increases your fit signal for the roles most likely to move through hiring quickly.
Confirm your visa category before the offer stage
Microsoft sponsors multiple visa types for this role, including H-1B and E-3 for Australian citizens. Clarify which category applies to your situation early, since E-3 processing moves faster and doesn't depend on the H-1B lottery.
Understand how Microsoft handles H-1B cap timing
If you need a cap-subject H-1B, your start date is tied to the USCIS lottery cycle. Microsoft typically coordinates offer timing around this, but you should know that a lottery miss means a 12-month wait before the next filing window opens.
Prepare for technical interviews that test systems design depth
Microsoft's senior DevOps interviews consistently include systems design rounds focused on large-scale distributed infrastructure. Sponsors invest in strong candidates, so demonstrating architectural thinking, not just scripting proficiency, directly affects whether an offer is extended.
Use Migrate Mate to find open Senior DevOps roles at Microsoft
Searching broadly wastes time on roles that don't sponsor. Use Migrate Mate to filter specifically for Senior DevOps Engineer openings at Microsoft that match your visa type, so you're applying where sponsorship is already confirmed.
Frequently Asked Questions
Does Microsoft sponsor H-1B visas for Senior Devops Engineers?
Yes, Microsoft sponsors H-1B visas for Senior DevOps Engineers. This role qualifies as a specialty occupation under USCIS standards, requiring at minimum a bachelor's degree in computer science, engineering, or a closely related field. If you're subject to the annual H-1B cap, timing your application around the USCIS lottery registration window in March is essential. Microsoft works with experienced immigration counsel to manage the filing process once an offer is extended.
How do I apply for Senior Devops Engineer jobs at Microsoft?
Applications go through Microsoft's careers portal, but browsing roles filtered by visa sponsorship eligibility is faster through Migrate Mate. Once you identify a matching role, the process involves an initial recruiter screen, a technical phone screen, and a full virtual interview loop covering systems design, coding, and behavioral rounds. Having your visa situation clearly understood before the offer stage avoids delays.
Which visa types does Microsoft commonly sponsor for Senior Devops Engineers?
Microsoft sponsors H-1B visas for most international candidates in this role. Australian citizens can pursue the E-3 visa, which has no lottery and allows faster processing through consular channels. For candidates already on an F-1 OPT or STEM OPT extension, Microsoft can file an H-1B petition before the OPT expires. Green Card sponsorship through EB-2 or EB-3 is also available for longer-tenured employees.
What qualifications does Microsoft expect for a Senior Devops Engineer role?
Microsoft's senior-level DevOps roles typically require significant hands-on experience with cloud infrastructure at scale, particularly on Azure. Proficiency in infrastructure-as-code tools like Terraform or Bicep, CI/CD pipeline design, and container orchestration with Kubernetes is expected. A bachelor's degree in computer science or a related engineering discipline is the baseline credential, and it also satisfies the specialty occupation requirement for H-1B visa purposes under USCIS guidelines.
How do I time my application if I need H-1B sponsorship at Microsoft?
The H-1B cap registration window opens in March each year, with approved petitions taking effect on October 1. If you're on F-1 STEM OPT, you have up to 24 months of buffer, which gives you runway to secure an offer and file. For candidates not on any current status, E-3 visa (if Australian) or H-1B1 visa (if Chilean or Singaporean) offer cap-exempt alternatives worth discussing directly with Microsoft's recruiting team.