Design Verification Engineer Jobs in Oregon
Design Verification Engineer jobs in Oregon concentrate in semiconductor design, consumer electronics, and advanced computing hardware, with Hillsboro, Portland, and Beaverton forming the state's densest hiring corridor. Intel, Lattice Semiconductor, and Cadence Design Systems maintain established engineering operations in the region and hire across the full seniority range from early-career verification engineers to principal-level specialists. The most in-demand specialties are functional verification using SystemVerilog and UVM, FPGA validation, and SoC-level verification. Find a role that fits below and apply directly.
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Showing 5 of 10+ Design Verification Engineer jobs
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.
The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the CSME team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for experienced engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Senior Physical Design Verification Engineer to join the team to support our mission and culture. This key role will impact the organization by helping deliver cutting edge silicon.
#SCHIE #CSME
Responsibilities
- Work closely with top level and block level Physical Design Engineers on analysis and fixes on LVS, DRC, ERC, Antenna, etc.
- Drive full chip integration for physical design verification, signoff and Tape-outs on the leading-edge technology nodes.
- Collaborating with clock, analog, integration team on definition, implementation, and verification of critical chip routing, power delivery, block integration and other aspects.
- Work with 3pIP and 1pIP teams for efficient and timely SOC-IP handshake.
- Work with CAD team, tool vendors, foundry and other external partners to develop and validate new tools, flows, runsets, etc.
- Utilize scripting/AI skills to write and customize tool flows to maximize design efficiency and productivity.
Qualifications
Required Qualifications:
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Other Requirements:
- Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
- This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred Qualifications:
- BS/MS in Electrical or Computer Engineering/Electrical Engineering
- 5+ years of experience in semiconductor chip design/SOC physical design.
- Experience in Physical Verification EDA tools like Mentor Calibre and Synopsys ICV.
- Debugging skills for DRC, LVS, ERC, Antenna, High Voltage DRC, ESD, etc.
- Multiple SOC Tape-Out experience in the advanced foundry process nodes.
- Understanding of full chip integration, floor planning, IO RDL and bump planning.
- Experience and knowledge of physical design flow and industry standard PNR tool (Fusion Compiler/Innovus, ICC2, etc.)
- Understanding of transistor/device basics.
- Proficient in scripting languages such as Perl, TCL, Python.
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process.
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.
The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the CSME team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for experienced engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Senior Physical Design Verification Engineer to join the team to support our mission and culture. This key role will impact the organization by helping deliver cutting edge silicon.
#SCHIE #CSME
Responsibilities
- Work closely with top level and block level Physical Design Engineers on analysis and fixes on LVS, DRC, ERC, Antenna, etc.
- Drive full chip integration for physical design verification, signoff and Tape-outs on the leading-edge technology nodes.
- Collaborating with clock, analog, integration team on definition, implementation, and verification of critical chip routing, power delivery, block integration and other aspects.
- Work with 3pIP and 1pIP teams for efficient and timely SOC-IP handshake.
- Work with CAD team, tool vendors, foundry and other external partners to develop and validate new tools, flows, runsets, etc.
- Utilize scripting/AI skills to write and customize tool flows to maximize design efficiency and productivity.
Qualifications
Required Qualifications:
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Other Requirements:
- Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
- This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred Qualifications:
- BS/MS in Electrical or Computer Engineering/Electrical Engineering
- 5+ years of experience in semiconductor chip design/SOC physical design.
- Experience in Physical Verification EDA tools like Mentor Calibre and Synopsys ICV.
- Debugging skills for DRC, LVS, ERC, Antenna, High Voltage DRC, ESD, etc.
- Multiple SOC Tape-Out experience in the advanced foundry process nodes.
- Understanding of full chip integration, floor planning, IO RDL and bump planning.
- Experience and knowledge of physical design flow and industry standard PNR tool (Fusion Compiler/Innovus, ICC2, etc.)
- Understanding of transistor/device basics.
- Proficient in scripting languages such as Perl, TCL, Python.
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process.
See All 10 Design Verification Engineer Jobs in Oregon
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Find JobsDesign Verification Engineer Jobs by City in Oregon
Where Oregon roles are concentrated, by current openings.
Design Verification Engineer Job Market in Oregon
A snapshot from current Oregon openings, updated as new roles post.
Who's Hiring
Top Industries Hiring
- Technology & Software
- Artificial Intelligence
- Electronics & Hardware
What Oregon Employers Look For
The qualifications that appear most often in design verification engineer jobs across Oregon.
- Bachelor's or master's degree in electrical engineering, computer engineering, or a related field
- Proficiency in SystemVerilog and Universal Verification Methodology for testbench development
- Experience writing and executing constrained-random and directed test plans for digital logic
- Familiarity with simulation tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa
- Ability to analyze coverage metrics and close functional coverage gaps independently
- Collaboration with RTL designers and firmware teams across full chip bring-up cycles
Design Verification Engineer Jobs in Oregon: Frequently Asked Questions
How do you become a design verification engineer in Oregon?
A bachelor's degree in electrical engineering, computer engineering, or computer science is the standard starting point for this role in Oregon, and many senior positions require or strongly prefer a master's degree. Oregon does not issue a state license specific to design verification engineers. Employers in the Hillsboro and Portland corridor typically expect hands-on experience with hardware description languages, simulation environments, and structured verification methodologies, which candidates build through coursework, internships, or adjacent roles in digital design.
Which companies hire design verification engineers in Oregon?
Oregon design verification engineer roles are posted by Apple, Google, and Microsoft and others right now, based on current listings on Migrate Mate as of November 2026. The heaviest concentration of postings is tied to Oregon's semiconductor corridor, where chip design activity from established fabs and IP companies generates consistent verification demand.
Which Oregon cities have the most design verification engineer jobs?
Beaverton, Portland, and Hillsboro account for the largest share of design verification engineer openings in Oregon. Hillsboro leads because Intel's large campus there drives substantial chip verification hiring, while Portland and Beaverton attract openings from semiconductor IP firms, EDA vendors, and hardware-focused startups clustered in the metro's west-side technology corridor.
Are there remote design verification engineer jobs in Oregon?
Yes, but they're limited compared to purely software roles, because much of the work involves lab access, simulation server environments, and hardware bring-up that require on-site presence at key milestones. About 50% of design verification engineer openings tied to Oregon are remote or hybrid as of November 2026, reflecting a modest but real subset of positions. Roles focused on testbench development, coverage analysis, and specification review are the most likely to support remote arrangements.
How can I get hired as a design verification engineer in Oregon with little or no experience?
The most realistic entry path is an internship or co-op with one of Oregon's semiconductor employers during a bachelor's or master's program, since companies like Intel in Hillsboro run structured university recruiting programs that convert to full-time offers. Candidates without internship experience can move laterally from adjacent roles in digital design, FPGA development, or embedded software testing, where verification skills overlap. Building a portfolio of SystemVerilog testbenches and UVM environments through coursework or open-source projects gives applicants a concrete edge when applying to new-grad positions.
Where can I find and apply to design verification engineer jobs in Oregon?
You can find and apply to design verification engineer jobs in Oregon on Migrate Mate, which lists current Oregon openings updated regularly. Search the listings for roles that match your experience level and target location, then apply directly to the ones that fit.
See All 10 Design Verification Engineer Jobs in Oregon
Find roles in Oregon that match your experience and apply in just a few clicks.
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