DFT Engineer Jobs
DFT Engineer jobs are open across semiconductor, fabless IC design, EDA, and consumer electronics, from new-grad to staff and principal levels, with specializations in ATPG, BIST, and boundary scan. See the openings below and apply to the ones that match your experience.
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Showing 5 of 99+ DFT Engineer jobs
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience in DFT architecture, implementation, and verification for SoCs.
- Experience in silicon bring-up, debug, or validation of DFT features.
- Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT).
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 10 years of experience in DFT architecture, implementation, and verification for SoCs.
- Experience with various fault models (e.g., Stuck-at, Transition, Cell-Aware, Path Delay, etc.).
- Experience in DFT flow, including architecture, IP integration (e.g., Test controllers, TAP, MBIST), and interaction with synthesis and verification flows.
- Experience with industry-leading EDA tools for DFT, such as Synopsys (e.g., Design Compiler, DFT Max) or Siemens EDA (e.g., Tessent, TestKompress).
- Knowledge of test standards (e.g., IEEE 1149.1, 1687) and test data Formats (e.g., BSDL, STIL).
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a DFT Engineer, you will be responsible for defining, implementing and deploying advanced design-for-test (DFT) methodologies including Scan, MBIST, JTAG and iJTAG, for highly digital or mixed-signal chips or IPs. You will define silicon test strategies, DFT/DFD architecture, and create DFT and Debug specifications for next generation SoCs. In partnership with the Silicon Engineering team, you will also be responsible for diagnosing memory and logic failures, increasing production quality, and enhancing yield and reducing test cost.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, MBIST, ATPG and I/JTAG, and associated boot up and execution sequences.
- Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high test quality.
- Develop diagnostic databases, software and hardware for logic and memory fail debug.
- Design and implement system level test strategy.
- Implement core DFT circuitry, including insertion and hook-up of scan chains, DFT compression, Logic BIST, TAP controllers, and Memory BIST (MBIST) logic for IP blocks.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience in DFT architecture, implementation, and verification for SoCs.
- Experience in silicon bring-up, debug, or validation of DFT features.
- Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT).
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 10 years of experience in DFT architecture, implementation, and verification for SoCs.
- Experience with various fault models (e.g., Stuck-at, Transition, Cell-Aware, Path Delay, etc.).
- Experience in DFT flow, including architecture, IP integration (e.g., Test controllers, TAP, MBIST), and interaction with synthesis and verification flows.
- Experience with industry-leading EDA tools for DFT, such as Synopsys (e.g., Design Compiler, DFT Max) or Siemens EDA (e.g., Tessent, TestKompress).
- Knowledge of test standards (e.g., IEEE 1149.1, 1687) and test data Formats (e.g., BSDL, STIL).
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a DFT Engineer, you will be responsible for defining, implementing and deploying advanced design-for-test (DFT) methodologies including Scan, MBIST, JTAG and iJTAG, for highly digital or mixed-signal chips or IPs. You will define silicon test strategies, DFT/DFD architecture, and create DFT and Debug specifications for next generation SoCs. In partnership with the Silicon Engineering team, you will also be responsible for diagnosing memory and logic failures, increasing production quality, and enhancing yield and reducing test cost.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, MBIST, ATPG and I/JTAG, and associated boot up and execution sequences.
- Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high test quality.
- Develop diagnostic databases, software and hardware for logic and memory fail debug.
- Design and implement system level test strategy.
- Implement core DFT circuitry, including insertion and hook-up of scan chains, DFT compression, Logic BIST, TAP controllers, and Memory BIST (MBIST) logic for IP blocks.
See All 99 DFT Engineer Jobs
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Who's Hiring
- Apple12
- Encore Semi9
- Cisco5
- SpaceX5
- Broadcom5
Top Industries Hiring
- Electronics & Hardware13
- Telecommunications2
- Aerospace & Defense2
- Technology & Software2
- Consulting & Professional Services1
What Employers Look For
The qualifications that appear most often in DFT engineer jobs.
- Bachelor's or master's degree in electrical engineering or computer engineering
- Hands-on experience with ATPG tools such as Synopsys TetraMAX, Cadence Modus, or Siemens Tessent
- Proficiency in scan insertion, BIST design, and boundary scan implementation
- Experience achieving and documenting stuck-at and transition fault coverage targets
- Familiarity with industry-standard test protocols including JTAG and IEEE 1500
- Scripting skills in Python, Tcl, or Perl for test flow automation and debug
Tips for Your DFT Engineer Job Search
Tailor your resume to tapeout milestones
DFT hiring managers scan for evidence of full-chip DFT closure. List specific tapeout projects, the nodes you worked on, and the fault coverage percentages you achieved rather than generic descriptions of tools or responsibilities.
List every ATPG tool you have used
Employers filter resumes by tool name. Call out Synopsys TetraMAX, Cadence Modus, Siemens Tessent, and any others explicitly in a skills section so your resume clears automated screening before a recruiter reads it.
Apply early to roles that fit
Migrate Mate lists dft engineer openings from across the United States in one place, so you can find roles that match and apply directly to each listing.
Target job descriptions that match your node experience
Many postings specify a process node range like 7nm to 3nm or legacy 28nm and above. Applying to roles that align with your actual node experience signals immediate productivity and dramatically improves your callback rate.
Prepare a fault-coverage walkthrough for interviews
DFT panels almost always ask you to walk through how you achieved target fault coverage on a real design. Rehearse a concise explanation of the tradeoffs you made between test time, pattern count, and area overhead on a chip you can discuss freely.
Negotiate test infrastructure ownership in your offer
Beyond title and compensation, clarify whether you will own DFT methodology decisions or execute someone else's flow. Knowing this upfront reveals the actual seniority of the role and gives you a concrete point to negotiate if the responsibility does not match the grade.
DFT Engineer Jobs: Frequently Asked Questions
Which companies are hiring the most dft engineers?
The most active employers for dft engineers right now are Apple, Encore Semi, and Cisco, and the most openings are in California, Texas, and Massachusetts, based on current listings on Migrate Mate as of November 2026. Semiconductor fabless companies and large integrated device manufacturers consistently post the highest volume of dft engineer roles.
How many dft engineer jobs are remote?
About 52% of dft engineer openings are fully remote or hybrid as of November 2026, reflecting the lab and tool-access constraints common in silicon design. Test methodology development and ATPG scripting roles tend to be the most remote-friendly, while positions requiring hands-on ATE bringup or silicon debug are more likely to require on-site presence.
How do you become a dft engineer?
Start with a degree in electrical or computer engineering with coursework in digital logic, VLSI design, and testing fundamentals. Build hands-on familiarity with at least one major ATPG tool through coursework, internships, or personal projects. Pursue entry-level IC design or verification roles that expose you to scan flows, then move toward dedicated DFT work as you gain tapeout experience.
How do you get hired as a dft engineer with little experience?
Focus on roles labeled DFT intern, junior DFT engineer, or physical implementation engineer at companies with structured new-grad programs. Demonstrate tool familiarity by completing free or academic licenses for ATPG software and documenting any scan or BIST work from coursework. Highlighting exposure to RTL simulation and synthesis shows the adjacent skills teams value when direct DFT experience is limited.
What does the dft engineer interview process look like?
Most DFT engineer interview processes include a recruiter screen, a technical phone round covering fault modeling and scan basics, and a full panel with the DFT team. The panel typically includes a design walkthrough where you describe a chip you worked on, a live coding or scripting exercise in Tcl or Python, and questions on fault coverage tradeoffs and test time reduction strategies.
Where can I find and apply to dft engineer jobs?
You can find and apply to dft engineer jobs on Migrate Mate, which lists current openings from across the United States. Search for roles that match your node experience, tool background, and seniority level, then apply directly to each listing that fits.
See All 99 DFT Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
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