Mid Level DFT Engineer Jobs
Mid level dft engineer jobs go to engineers ready to own test blocks end to end, champion DFT methodology decisions, and mentor junior team members with minimal oversight. Roles are concentrated across Aerospace & Defense, Technology & Software, and Electronics & Hardware, with a mix of on-site and hybrid settings, and employers like SpaceX, Broadcom, and Apple are hiring at this level now.
Find Mid Level DFT Engineer JobsOverview
Showing 5 of 6+ Mid Level DFT Engineer jobs
INTRODUCTION
Broadcom's ASIC Product Division is seeking candidates for a DFT position at our Austin, Texas Development Center. The successful candidate will work on DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production.
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Products Division)’s designs – DFT Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.
It is expected that you can code using TCL, PERL, RUBY, PYTHON, C++ or similar.
Responsibilities
- Understanding Broadcom & customer DFT feature requirements
- Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
- Working closely with STA and DI Engineers design closure for test
- Generating, Verifying & Debugging Test vectors before tape release
- Validating & Debugging Test vectors on ATE during the silicon bring up phase
- Assisting with silicon failure analysis, diagnostics & yield improvement efforts
- Interfacing with the customer, physical design and test engineering/manufacturing teams located globally
- Working closely with I/P DFT engineers & other stakeholders
- Debugging customer returned parts on the ATE
BASIC QUALIFICATIONS
- Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
- Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, SSN etc.)
- Well-versed in ATPG vector generation, simulation, and debugging (TetraMax, Fastscan)
- Experience in Verilog coding, testbench generation & simulation
- Memory BIST insertion and verification experience on embedded (SRAM, CAM, eDRAM, ROM)
- Boundary scan Verification and test vector generation. Should have good knowledge in IEEE1149.1 and IEEE1149.6
- Basic knowledge of Test-STA and constraints
- Strong background on IEE1687, IJTAG, ICL and PDL, SSN
- The ability to work in a multi-disciplined, cross-department environment
- Solid knowledge in analog and digital circuit design, and device physics fundamentals
- Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles
- Excellent problem solving, debug, root cause analysis and communication skills
EDUCATION & EXPERIENCE
Bachelors in Electrical/Electronic/Computer Engineering and 5+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 3+ years of relevant industry experience
COMPENSATION AND BENEFITS
The annual base salary range for this position is USD To USD
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
INTRODUCTION
Broadcom's ASIC Product Division is seeking candidates for a DFT position at our Austin, Texas Development Center. The successful candidate will work on DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production.
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Products Division)’s designs – DFT Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.
It is expected that you can code using TCL, PERL, RUBY, PYTHON, C++ or similar.
Responsibilities
- Understanding Broadcom & customer DFT feature requirements
- Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
- Working closely with STA and DI Engineers design closure for test
- Generating, Verifying & Debugging Test vectors before tape release
- Validating & Debugging Test vectors on ATE during the silicon bring up phase
- Assisting with silicon failure analysis, diagnostics & yield improvement efforts
- Interfacing with the customer, physical design and test engineering/manufacturing teams located globally
- Working closely with I/P DFT engineers & other stakeholders
- Debugging customer returned parts on the ATE
BASIC QUALIFICATIONS
- Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
- Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, SSN etc.)
- Well-versed in ATPG vector generation, simulation, and debugging (TetraMax, Fastscan)
- Experience in Verilog coding, testbench generation & simulation
- Memory BIST insertion and verification experience on embedded (SRAM, CAM, eDRAM, ROM)
- Boundary scan Verification and test vector generation. Should have good knowledge in IEEE1149.1 and IEEE1149.6
- Basic knowledge of Test-STA and constraints
- Strong background on IEE1687, IJTAG, ICL and PDL, SSN
- The ability to work in a multi-disciplined, cross-department environment
- Solid knowledge in analog and digital circuit design, and device physics fundamentals
- Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles
- Excellent problem solving, debug, root cause analysis and communication skills
EDUCATION & EXPERIENCE
Bachelors in Electrical/Electronic/Computer Engineering and 5+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 3+ years of relevant industry experience
COMPENSATION AND BENEFITS
The annual base salary range for this position is USD To USD
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
See All 6 Mid Level DFT Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
Find Mid Level DFT Engineer JobsMid Level DFT Engineer Job Market
Who's Hiring
Top Industries Hiring
- Aerospace & Defense
- Technology & Software
- Electronics & Hardware
Mid Level DFT Engineer Jobs: Frequently Asked Questions
How do I get a mid level dft engineer job?
Position yourself around ownership, not just contribution. Highlight projects where you drove DFT methodology choices, debugged scan or BIST failures independently, or improved test coverage metrics. Tailor your resume to show depth in at least one area, such as ATPG, boundary scan, or silicon bring-up, and be ready to walk through your diagnostic reasoning in technical interviews.
Which companies hire mid level dft engineers?
Companies hiring mid level dft engineers right now include SpaceX, Broadcom, and Apple, based on current listings on Migrate Mate as of November 2026. Hiring at this level comes from semiconductor fabless companies, integrated device manufacturers, and large technology firms with in-house silicon design teams.
Are there remote mid level dft engineer jobs?
Yes, though on-site and hybrid arrangements remain common given the lab and EDA tool access the work often requires. About 0% of mid level dft engineer openings are remote or hybrid as of November 2026, so options exist depending on the company and project phase you would be joining.
How do I move up to a mid level dft engineer role?
Moving into mid level comes from building consistent ownership over two to four years of hands-on work. Focus on deepening expertise in specific DFT flows, taking initiative on debugging and coverage closure without waiting to be directed, and demonstrating that your decisions have improved tape-out readiness or reduced test time on real products.
Which industries hire the most mid level dft engineers?
Mid Level dft engineer roles concentrate in Aerospace & Defense, Technology & Software, and Electronics & Hardware, based on current listings on Migrate Mate as of November 2026. These sectors drive hiring at this level because they invest heavily in custom silicon development, where DFT expertise is essential to achieving acceptable yield and reducing manufacturing test costs.