Packaging Engineer Jobs in California
Packaging Engineer jobs in California are in strong demand, with active hiring concentrated in food and beverage manufacturing, consumer goods, pharmaceuticals, and e-commerce fulfillment, roles available from entry-level packaging technologist through senior principal engineer. The busiest hiring markets are the Los Angeles Basin, the San Francisco Bay Area, and Sacramento, where established employers such as Gallo, Gilead Sciences, and Amazon maintain significant packaging operations. Specialties seeing the most consistent California demand include sustainable packaging design, materials engineering, and automation-integrated production systems. Find a role that fits below and apply directly.
Find Packaging Engineer JobsOverview
Showing 5 of 83+ Packaging Engineer jobs
Company:
Qualcomm Technologies, Inc.Job Area:
Engineering Group, Engineering Group > Packaging EngineeringGeneral Summary:
The engineer will be a key member of the Process Package Integration and bumping process team, driving technology development and new product introduction (NPI) with primary ownership of wafer bumping (Far-BEOL) process integration, qualification, and high-volume readiness across multiple silicon technology nodes, foundries, bumping lines, and assembly houses (OSATs). Key responsibilities include defining bumping process flows (passivation/UBM/RDL/bump), establishing process windows and controls, leading DOE-based optimization, and partnering with suppliers to improve yield, reliability, and cost. The role works closely with foundry FBEOL teams, bumping/assembly partners, and internal package design, process, quality, test, and product development teams to deliver robust bumping solutions enabling advanced packaging (flip-chip, RDL/fan-out, and 2.5D/3DIC). The candidate will also lead bumping house/line bring-up, qualification, and ongoing performance management to expand capacity and ensure multi-source readiness.
Skill/Knowledge:
- Expertise in Far-BEOL bumping process modules and integration, including passivation openings, UBM, RDL (as applicable), solder/Cu pillar bump formation, and associated materials/equipment.
- Deep knowledge of flip-chip bump design intent and assembly interactions (bump metallurgy, pitch scaling, coplanarity, warpage interactions), and wafer-level packaging (RDL) / fan-out process considerations impacting bumping.
- Strong technical skills in bumping process/material/equipment characterization (metrology and inline controls), failure analysis, DOE design, statistical data analysis, and FMEA to drive yield and reliability improvements.
- Experience leading bumping process qualification and production release activities (process window definition, control plans/SPC, GR&R, and risk mitigation) for NPI and high-volume manufacturing.
- Proven track record enabling package development through robust bumping solutions for flip-chip, RDL/fan-out RDL, and advanced packaging technologies (2.5D/3DIC).
- Expertise in manufacturing execution for Far-BEOL bump structures and bump line operations, including new bumping line bring-up, tooling/equipment qualification, and production ramp (HVM readiness).
- Hands-on experience in project leadership and supplier management for external bumping houses/OSATs, including KPI definition, yield excursions containment, and continuous improvement programs.
- Experienced interfacing with foundries and bumping houses on process integration, change control, line qualification, and multi-source/capacity expansion.
- Understanding of heterogeneous integration (2.5D/3DIC) packaging flows and how bumping/interconnect schemes (micro-bumps, fine-pitch RDL) impact downstream assembly and reliability.
- Ability to design and drive novel test vehicles/structures for bump/RDL process characterization and process-package interaction (reliability, electromigration, mechanical integrity).
- Experience with chip and substrate design tools such as Calibre, Virtuoso, CAD, SiP, and GDS.
- Understanding of chip-top physical design flow and communication with package design teams.
- Minimum of 8–10 years hands-on experience in silicon interconnect process, bumping and/or RDL process, new technology qualification and production.
Additional Skills
- Good analytical and project management skills.
- Excellent capability of innovation and creativity.
- Highly motivated and committed to success of the individual and the team.
- Superior interpersonal communication skills. Publish technical reports.
- Able to work flexible hours. Occasional domestic/international travels needed.
Minimum Qualifications:
- Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 6+ years of System/Package Design/Technology Engineering or related work experience.
Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 5+ years of System/Package Design/Technology Engineering or related work experience.
OR
PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 4+ year of System/Package Design/Technology Engineering or related work experience.
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
Pay range and Other Compensation & Benefits :
$191,800.00 - $287,800.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link .
If you would like more information about this role, please contact Qualcomm Careers .
Company:
Qualcomm Technologies, Inc.Job Area:
Engineering Group, Engineering Group > Packaging EngineeringGeneral Summary:
The engineer will be a key member of the Process Package Integration and bumping process team, driving technology development and new product introduction (NPI) with primary ownership of wafer bumping (Far-BEOL) process integration, qualification, and high-volume readiness across multiple silicon technology nodes, foundries, bumping lines, and assembly houses (OSATs). Key responsibilities include defining bumping process flows (passivation/UBM/RDL/bump), establishing process windows and controls, leading DOE-based optimization, and partnering with suppliers to improve yield, reliability, and cost. The role works closely with foundry FBEOL teams, bumping/assembly partners, and internal package design, process, quality, test, and product development teams to deliver robust bumping solutions enabling advanced packaging (flip-chip, RDL/fan-out, and 2.5D/3DIC). The candidate will also lead bumping house/line bring-up, qualification, and ongoing performance management to expand capacity and ensure multi-source readiness.
Skill/Knowledge:
- Expertise in Far-BEOL bumping process modules and integration, including passivation openings, UBM, RDL (as applicable), solder/Cu pillar bump formation, and associated materials/equipment.
- Deep knowledge of flip-chip bump design intent and assembly interactions (bump metallurgy, pitch scaling, coplanarity, warpage interactions), and wafer-level packaging (RDL) / fan-out process considerations impacting bumping.
- Strong technical skills in bumping process/material/equipment characterization (metrology and inline controls), failure analysis, DOE design, statistical data analysis, and FMEA to drive yield and reliability improvements.
- Experience leading bumping process qualification and production release activities (process window definition, control plans/SPC, GR&R, and risk mitigation) for NPI and high-volume manufacturing.
- Proven track record enabling package development through robust bumping solutions for flip-chip, RDL/fan-out RDL, and advanced packaging technologies (2.5D/3DIC).
- Expertise in manufacturing execution for Far-BEOL bump structures and bump line operations, including new bumping line bring-up, tooling/equipment qualification, and production ramp (HVM readiness).
- Hands-on experience in project leadership and supplier management for external bumping houses/OSATs, including KPI definition, yield excursions containment, and continuous improvement programs.
- Experienced interfacing with foundries and bumping houses on process integration, change control, line qualification, and multi-source/capacity expansion.
- Understanding of heterogeneous integration (2.5D/3DIC) packaging flows and how bumping/interconnect schemes (micro-bumps, fine-pitch RDL) impact downstream assembly and reliability.
- Ability to design and drive novel test vehicles/structures for bump/RDL process characterization and process-package interaction (reliability, electromigration, mechanical integrity).
- Experience with chip and substrate design tools such as Calibre, Virtuoso, CAD, SiP, and GDS.
- Understanding of chip-top physical design flow and communication with package design teams.
- Minimum of 8–10 years hands-on experience in silicon interconnect process, bumping and/or RDL process, new technology qualification and production.
Additional Skills
- Good analytical and project management skills.
- Excellent capability of innovation and creativity.
- Highly motivated and committed to success of the individual and the team.
- Superior interpersonal communication skills. Publish technical reports.
- Able to work flexible hours. Occasional domestic/international travels needed.
Minimum Qualifications:
- Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 6+ years of System/Package Design/Technology Engineering or related work experience.
Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 5+ years of System/Package Design/Technology Engineering or related work experience.
OR
PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 4+ year of System/Package Design/Technology Engineering or related work experience.
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
Pay range and Other Compensation & Benefits :
$191,800.00 - $287,800.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link .
If you would like more information about this role, please contact Qualcomm Careers .
See All 83 Packaging Engineer Jobs in California
Find roles in California that match your experience and apply in just a few clicks.
Find Packaging Engineer JobsPackaging Engineer Jobs by City in California
Where California roles are concentrated, by current openings.
Packaging Engineer Job Market in California
A snapshot from current California openings, updated as new roles post.
Who's Hiring
Top Industries Hiring
- Electronics & Hardware15
- Technology & Software7
- Telecommunications5
- Manufacturing4
- Food & Beverage1
What California Employers Look For
The qualifications that appear most often in packaging engineer jobs across California.
- Bachelor's degree in packaging science, mechanical engineering, or a closely related field
- Experience with packaging materials such as corrugated, flexible film, and rigid plastics
- Proficiency in CAD software for structural packaging design and prototyping
- Familiarity with ASTM, ISTA, or TAPPI testing standards for packaging validation
- Knowledge of FDA regulations for packaging used in food, beverage, or pharmaceutical applications
- Experience collaborating with supply chain, manufacturing, and marketing teams on product launches
Packaging Engineer Jobs in California: Frequently Asked Questions
How do you become a packaging engineer in California?
Most packaging engineer roles in California require a bachelor's degree in packaging science, mechanical engineering, materials science, or a related field, California State Polytechnic University, San Luis Obispo offers one of the few dedicated packaging engineering programs in the state. California does not require a state-issued license specific to packaging engineering, though engineers who take on broader project engineering responsibilities may pursue Professional Engineer registration through the California Board for Professional Engineers, Land Surveyors, and Geologists.
Which companies hire packaging engineers in California?
Employers hiring packaging engineers in California right now include Nokia, Qualcomm, and Skyworks Solutions, based on current listings on Migrate Mate as of September 2026. California's dense concentration of food and beverage producers, consumer packaged goods brands, and life sciences companies means packaging engineers here work across a broader range of regulated and unregulated product categories than in most other states.
Which California cities have the most packaging engineer jobs?
Sunnyvale, San Diego, and Irvine have the most packaging engineer openings in California. Los Angeles anchors hiring through its massive consumer goods and e-commerce distribution sector, the Bay Area draws demand from food tech startups and pharmaceutical firms, and Sacramento's location near the Central Valley's agricultural processing industry supports steady openings outside the major coastal metros.
Are there remote packaging engineer jobs in California?
Yes, but they're rare. Packaging engineering is fundamentally a hands-on role, prototype evaluation, line trials, and materials testing typically require on-site presence. About 37% of packaging engineer openings tied to California are remote or hybrid as of September 2026, and those positions tend to concentrate in specification writing, supplier qualification, and project coordination work that can be done away from the production floor.
How can I get hired as a packaging engineer in California with little or no experience?
The most realistic entry path is an internship or co-op secured during a packaging science or engineering program, particularly through Cal Poly San Luis Obispo's industry-connected curriculum. Large California food and consumer goods manufacturers such as Gallo and McCormick run structured new-graduate rotational programs, and many life sciences companies hire entry-level packaging associates who move into engineer roles after learning validation and compliance workflows. Candidates without a packaging-specific degree can also transition from adjacent roles in manufacturing engineering, quality assurance, or industrial design, especially with an Institute of Packaging Professionals certification.
Where can I find and apply to packaging engineer jobs in California?
You can find and apply to packaging engineer jobs in California on Migrate Mate, which lists current California openings updated regularly. Find the roles that fit your background and apply directly from the listing.
See All 83 Packaging Engineer Jobs in California
Find roles in California that match your experience and apply in just a few clicks.
Find Packaging Engineer Jobs