Principal Engineer Jobs in San Jose, CA
Principal Engineer jobs in San Jose are in strong demand, concentrated in North San Jose, Downtown, and the Santana Row corridor across semiconductor, enterprise software, and networking hardware sectors. Companies actively hiring include Cadence Design Systems, Zscaler, and Collins Aerospace. Scan the live roles below and apply to whichever ones fit.
Find Principal Engineer JobsOverview
Open roles906+
Top employerCadence Design Systems
Work type67% Hybrid
Top credentialBachelor's degree in electrical engineering
Companies hiring45
Showing 5 of 906+ Principal Engineer jobs
Principal Engineer, Advanced Packaging
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Added 1d ago
Ayar Labs
Principal Engineer, Advanced Packaging
San Jose, California
Added 1d ago
Principal GenAI Data Engineer
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Added 2d ago
Zscaler
Principal GenAI Data Engineer
San Jose, California
Added 2d ago
Principal Software Engineer
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Added 2d ago
Index Engines
Principal Software Engineer
San Jose, California
Added 2d ago
Senior Principal Digital SoC Design Engineer
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Added 2d ago
MaxLinear Inc.
Senior Principal Digital SoC Design Engineer
San Jose, California
Added 2d ago
Principal Systems Software Engineer
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Added 3d ago
NetApp
Principal Systems Software Engineer
San Jose, California
Added 3d ago
Added 1d ago
Principal Engineer, Advanced Packaging
Ayar Labs·San Jose, California
Job functions:
$224k - $261k/yr
On-Site
Military encouraged
Job Description
Principal / Senior Principal Engineer, Advanced Packaging
Location: San Jose, CA (on-site)
Location: San Jose, CA (on-site)
Ayar Labs, the global leader in optical I/O chiplets, is harnessing silicon photonics to revolutionize the scaling of AI compute hardware. Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.
Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.
Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.
Ayar Labs is seeking a Principal or Senior Principal Advanced Packaging Engineer to help shape the Co-Packaged Optics revolution in High-Performance Computing.
The primary responsibility of the Advanced Packaging Engineer is to define an advanced packaging technology roadmap, enabling the transition from successful design of validation systems to incorporation into high-volume manufacturing. The Advanced Packaging Engineer is expected to drive the electrical package engineering team to success with first principles, collaboration and discipline.
Prior experience in photonics is not necessary; however, the candidate must display a propensity for growth. The exceptional candidate must be highly motivated and energetic, willing to collaborate with diverse, cross-functional teams. This is an on-site role in Ayar Labs’ San Jose Headquarter office.
Essential Functions
- Design and develop the package architecture from silicon validation to high-volume product adoption.
- Maintain technical documentation for delivery to vendors, manufacturing partners and customers.
- Provide mentorship to engineering staff throughout project execution.
- Collaborate with engineering and program management to make accurate risk assessments, driving critical project schedules.
- Coordinate with internal and external stakeholders including Reliability, Silicon Engineering, Validation, Design Service Vendors, substrate suppliers, and OSAT/assembly partners.
- Ensure appropriate standards for DFM, DFA, and DFR (design-for-manufacturability, -assembly, and -reliability) are met for all package deliverables.
- Define package-level specifications for high-speed electrical interfaces, including SerDes, PCIe, and die-to-die (D2D) interconnects.
- Define company standards for power distribution network (PDN) design, simulation and verification.
Basic Qualifications
- Advanced degree in Electrical Engineering or related field plus 12+ years (15+ years for Senior Principal) of industry experience.
- Demonstrated experience in the design and validation of advanced package technology for SerDes, PCIe, die-to-die (D2D) interconnects, HPC .
- Expert in Power and Signal Integrity analysis and design, with proficiency in at least one major simulation tool (e.g., Ansys HFSS, SIwave, Cadence Clarity, PowerSI).
- Strong understanding of warpage, thermal and mechanical analysis of substrate technology.
- Exceptional technical communication skills.
Preferred Qualifications
- Experience in the design of high-power advanced package designs (>1kW).
- Experience in optical transceiver design and validation, especially co-packaged optics.
- Experience using agentic design and verification workflows (e.g., AI-assisted simulation setup, layout checking, or documentation generation).
- Track record of new product introduction (NPI), from concept through development and production release.
- Familiarity with JEDEC and other industry reliability/qualification standards.
Salary Range: $224,000 - $261,000
NOTE TO RECRUITERS:
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.
Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.
Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.
Ayar Labs
Principal Engineer, Advanced Packaging
San Jose, California
Added 1d ago
Job functions:
$224k - $261k/yr
On-Site
Military encouraged
Job Description
Principal / Senior Principal Engineer, Advanced Packaging
Location: San Jose, CA (on-site)
Location: San Jose, CA (on-site)
Ayar Labs, the global leader in optical I/O chiplets, is harnessing silicon photonics to revolutionize the scaling of AI compute hardware. Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.
Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.
Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.
Ayar Labs is seeking a Principal or Senior Principal Advanced Packaging Engineer to help shape the Co-Packaged Optics revolution in High-Performance Computing.
The primary responsibility of the Advanced Packaging Engineer is to define an advanced packaging technology roadmap, enabling the transition from successful design of validation systems to incorporation into high-volume manufacturing. The Advanced Packaging Engineer is expected to drive the electrical package engineering team to success with first principles, collaboration and discipline.
Prior experience in photonics is not necessary; however, the candidate must display a propensity for growth. The exceptional candidate must be highly motivated and energetic, willing to collaborate with diverse, cross-functional teams. This is an on-site role in Ayar Labs’ San Jose Headquarter office.
Essential Functions
- Design and develop the package architecture from silicon validation to high-volume product adoption.
- Maintain technical documentation for delivery to vendors, manufacturing partners and customers.
- Provide mentorship to engineering staff throughout project execution.
- Collaborate with engineering and program management to make accurate risk assessments, driving critical project schedules.
- Coordinate with internal and external stakeholders including Reliability, Silicon Engineering, Validation, Design Service Vendors, substrate suppliers, and OSAT/assembly partners.
- Ensure appropriate standards for DFM, DFA, and DFR (design-for-manufacturability, -assembly, and -reliability) are met for all package deliverables.
- Define package-level specifications for high-speed electrical interfaces, including SerDes, PCIe, and die-to-die (D2D) interconnects.
- Define company standards for power distribution network (PDN) design, simulation and verification.
Basic Qualifications
- Advanced degree in Electrical Engineering or related field plus 12+ years (15+ years for Senior Principal) of industry experience.
- Demonstrated experience in the design and validation of advanced package technology for SerDes, PCIe, die-to-die (D2D) interconnects, HPC .
- Expert in Power and Signal Integrity analysis and design, with proficiency in at least one major simulation tool (e.g., Ansys HFSS, SIwave, Cadence Clarity, PowerSI).
- Strong understanding of warpage, thermal and mechanical analysis of substrate technology.
- Exceptional technical communication skills.
Preferred Qualifications
- Experience in the design of high-power advanced package designs (>1kW).
- Experience in optical transceiver design and validation, especially co-packaged optics.
- Experience using agentic design and verification workflows (e.g., AI-assisted simulation setup, layout checking, or documentation generation).
- Track record of new product introduction (NPI), from concept through development and production release.
- Familiarity with JEDEC and other industry reliability/qualification standards.
Salary Range: $224,000 - $261,000
NOTE TO RECRUITERS:
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.
Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.
Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.
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Find Principal Engineer JobsPrincipal Engineer Job Market in San Jose
Who's Hiring
- Cadence Design Systems70
- Zscaler53
- Collins Aerospace53
- Renesas44
- Ayar Labs44
Top Industries Hiring
- Electronics & Hardware
- Technology & Software
Principal Engineer Jobs in San Jose: Frequently Asked Questions
How do I get a principal engineer job in San Jose?
Target the semiconductor, enterprise software, and networking hardware companies concentrated in North San Jose and the Alviso corridor, where the density of principal engineer openings is highest. Candidates with system architecture experience, a record of leading cross-functional technical decisions, and familiarity with large-scale distributed systems stand out. Engaging with San Jose's deep network of engineering meetups and alumni groups at nearby research universities can open doors faster than cold applications.
Which companies hire principal engineers in San Jose?
San Jose principal engineer roles are posted by Cadence Design Systems, Zscaler, and Collins Aerospace and others right now, based on current listings on Migrate Mate as of November 2026. San Jose's hiring base skews heavily toward established semiconductor firms, enterprise infrastructure companies, and large-scale cloud platform providers with significant engineering campuses in the city.
Are there remote principal engineer jobs in San Jose?
Yes, though availability depends heavily on the role: principal engineers in software architecture and platform engineering often work remotely, while those in hardware, semiconductor design, or lab-adjacent work are almost always on-site. About 82% of principal engineer openings tied to San Jose are remote or hybrid as of November 2026, with the strongest remote options concentrated in software infrastructure and cloud platform teams.
How can I get a principal engineer job in San Jose with little or no experience?
The most realistic entry path is landing a senior software engineer or staff engineer role at one of San Jose's mid-size enterprise software or semiconductor firms, then building toward principal-level scope internally. Companies in the North San Jose tech corridor frequently promote from within and often prefer candidates who have grown through their engineering ladder. Contributing to open-source projects widely used in the networking or storage space, which are well-represented in San Jose, adds credibility that accelerates that progression.
Which industries hire the most principal engineers in San Jose?
Most principal engineer openings in San Jose sit in Electronics & Hardware and Technology & Software, per current listings on Migrate Mate as of November 2026. San Jose's position as the center of Silicon Valley's semiconductor and enterprise networking industries means demand for principal-level technical leadership is driven primarily by companies building complex, long-cycle hardware and software systems rather than consumer applications.
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