Remote ASIC Design Engineer Jobs
Remote ASIC Design Engineer jobs are open across semiconductor, defense electronics, and consumer hardware sectors at chip design firms, fabless startups, and distributed engineering teams. Employers hiring remotely right now include K2 Space, Positron AI, and Tensordyne. Scan the live roles below and apply to whichever ones fit.
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Showing 5 of 13+ Remote ASIC Design Engineer jobs
K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.
The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.
With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.
The Role
We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon.
Responsibilities
- Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
- Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
- Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
- Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
- Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
- Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
- Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
- Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
- Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
- Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
- Participate in ASIC team interviews.
- Drive advancement of DV methodologies and improvements.
- Manage external IP providers and verification partners when needed.
- Take lead on large and/or complex systems.
Qualifications
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
- 10+ years of experience in ASIC/SoC verification.
- Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
- Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
- Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
- Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
- Experience with developing and integrating reference models.
- Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
- Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
- Involvement in post-silicon validation planning and execution.
Nice to Have
- Experience with low power verification.
- Experience with analog behavioral models.
- Familiarity with physical design flows.
- Experience working in cross-functional, geographically distributed teams.
- Experience in space, telecom, or RF/digital mixed systems is a plus.
Compensation and Benefits:
- Base salary range for this role is $190,000 – $285,000 + equity in the company
- Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
- Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!
If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.
Export Compliance
As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."
The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
Equal Opportunity
K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.
The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.
With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.
The Role
We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon.
Responsibilities
- Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
- Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
- Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
- Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
- Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
- Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
- Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
- Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
- Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
- Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
- Participate in ASIC team interviews.
- Drive advancement of DV methodologies and improvements.
- Manage external IP providers and verification partners when needed.
- Take lead on large and/or complex systems.
Qualifications
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
- 10+ years of experience in ASIC/SoC verification.
- Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
- Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
- Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
- Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
- Experience with developing and integrating reference models.
- Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
- Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
- Involvement in post-silicon validation planning and execution.
Nice to Have
- Experience with low power verification.
- Experience with analog behavioral models.
- Familiarity with physical design flows.
- Experience working in cross-functional, geographically distributed teams.
- Experience in space, telecom, or RF/digital mixed systems is a plus.
Compensation and Benefits:
- Base salary range for this role is $190,000 – $285,000 + equity in the company
- Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
- Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!
If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.
Export Compliance
As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."
The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
Equal Opportunity
K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
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Find JobsRemote ASIC Design Engineer Job Market
Who's Hiring
What Employers Look For
The qualifications that appear most often in remote ASIC design engineer jobs.
- Bachelor's or master's degree in electrical engineering or computer engineering
- Proficiency in RTL design using Verilog or SystemVerilog
- Experience with synthesis and static timing analysis using Synopsys or Cadence tools
- Hands-on experience with digital verification methodologies including UVM or SystemVerilog assertions
- Familiarity with physical design flows including floorplanning, place and route, and signoff
- Experience taping out designs at a commercial foundry process node
Tips for Your Remote ASIC Design Engineer Job Search
Show your tape-out experience upfront
Remote asic design engineer roles move fast, and hiring managers scan for concrete evidence of delivery. List every tape-out you contributed to, the process node, your specific role in the RTL-to-GDSII flow, and the EDA tools you used. That specificity replaces the in-person credibility check.
Demonstrate async communication before the interview
Remote chip design teams depend on written clarity because design reviews happen across time zones in Confluence pages and email threads, not whiteboards. Write your application materials and any take-home tasks as if the reader can't ask a follow-up question, because often they can't.
Apply early to remote roles that fit
Migrate Mate lists remote asic design engineer openings from across the U.S. in one place so you can find roles that match your EDA stack and apply directly without digging through general job boards. Apply as soon as a role goes live since distributed teams often close postings quickly.
Prepare for remote-first technical interviews
Remote employers frequently run live RTL coding sessions in browser-based HDL sandboxes or shared EDA environments instead of a whiteboard. Practice writing synthesizable Verilog or VHDL under time pressure in a plain text editor so the tool gap doesn't slow you down on the call.
Remote ASIC Design Engineer Jobs: Frequently Asked Questions
How do I get a remote asic design engineer job?
Target fabless semiconductor companies and defense electronics firms that run distributed design teams, since those employers have the infrastructure to onboard remote hardware engineers. Remote hiring managers screen heavily for RTL design proficiency, familiarity with industry-standard EDA tools, and the ability to document design decisions clearly in writing. Candidates who can share prior tape-out experience, a clean GitHub repository of HDL projects, or contributions to an open-source chip project stand out when no one can watch you work in person.
Which companies hire remote asic design engineers?
Companies hiring remote asic design engineers right now include K2 Space, Positron AI, and Tensordyne, based on current remote listings on Migrate Mate as of November 2026. Remote openings for this role concentrate at fabless chip companies, defense contractors with distributed engineering teams, and semiconductor IP licensing firms that operate across multiple time zones.
Can you get a remote asic design engineer job with no experience?
Yes, but remote entry-level roles are harder to land because employers expect you to debug independently without a senior engineer at the next desk. Your strongest path is building an HDL project portfolio, contributing to open-source RISC-V or FPGA repositories, and completing a hands-on digital design course you can point to. Smaller fabless startups and academic spinouts are the most likely to give a junior candidate a remote shot when the work product speaks for itself.
Do you need a degree for remote asic design engineer jobs?
Usually, but demonstrated skills carry significant weight alongside it. Most remote employers in this field expect at least a bachelor's in electrical engineering or computer engineering given the depth of RTL, verification, and physical design knowledge required. That said, candidates who can show completed tape-outs, strong EDA tool fluency, or a detailed HDL portfolio can sometimes offset a non-traditional educational background, particularly at startups evaluating practical output over credentials.
See All 13 Remote ASIC Design Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
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