ASIC Design Engineer Jobs
ASIC Design Engineer jobs are open from new-grad to principal and staff levels across semiconductor companies, fabless chip design firms, and consumer electronics manufacturers, with specializations in RTL design, physical design, and verification. See the openings below and apply to the ones that match your experience.
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Showing 5 of 281+ ASIC Design Engineer jobs
The application window is expected to close on: 09/01/2026. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Meet the team:
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Your Impact:
Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Design, document, and develop ASIC subsystems for release in high volume and quality. Help define the process, methods, and tools for design and implementation of complex developments.
Key Responsibilities:
- Responsible for development of the comprehensive DFx & test solutions and architectures that support ATE screening, in-system test, debug and diagnostics needs of the design.
- Lead the RTL implementation from the architecture specifications and required RTL quality checks implementations.
- Work with the team on Innovative Hardware DFx & test strategy aspects for leading edge technology nodes and packaging styles, driving re-usable test and debug methodologies and standards.
Minimum Qualifications:
- Bachelor's on Electrical Engineering with 10+ years (or Master’s with 8+ years) of experience on ASIC hardware development.
- Prior experience with ASIC DFx and test relevant standards, and techniques.
- Prior experience with silicon life cycle, including manufacturing screening and qualification.
- Prior experience on ASIC components including high speed IO’s and their test + diagnosis solutions.
Preferred Qualifications:
- Prior experience on hardware design specifications and verification plan/matrix.
- Prior experience on RTL QA checks, including lint & CDC.
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Message to applicants applying to work in the U.S. and/or Canada:
The starting salary range posted for this position is $210,600.00 to $305,100.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.
U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:
- 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees.
- 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco.
- Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees.
- Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations).
- 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next.
- Additional paid time away may be requested to deal with critical or emergency issues for family members.
- Optional 10 paid days per full calendar year to volunteer.
For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:
- .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
- 1.5% of incentive target for each 1% of attainment between 50% and 75%;
- 1% of incentive target for each 1% of attainment between 75% and 100%; and
- Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.
The applicable full salary ranges for this position, by specific state, are listed below:
New York City Metro Area:
$210,600.00 - $350,800.00
Non-Metro New York state & Washington state:
$189,300.00 - $312,200.00
- For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.
The application window is expected to close on: 09/01/2026. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Meet the team:
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Your Impact:
Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Design, document, and develop ASIC subsystems for release in high volume and quality. Help define the process, methods, and tools for design and implementation of complex developments.
Key Responsibilities:
- Responsible for development of the comprehensive DFx & test solutions and architectures that support ATE screening, in-system test, debug and diagnostics needs of the design.
- Lead the RTL implementation from the architecture specifications and required RTL quality checks implementations.
- Work with the team on Innovative Hardware DFx & test strategy aspects for leading edge technology nodes and packaging styles, driving re-usable test and debug methodologies and standards.
Minimum Qualifications:
- Bachelor's on Electrical Engineering with 10+ years (or Master’s with 8+ years) of experience on ASIC hardware development.
- Prior experience with ASIC DFx and test relevant standards, and techniques.
- Prior experience with silicon life cycle, including manufacturing screening and qualification.
- Prior experience on ASIC components including high speed IO’s and their test + diagnosis solutions.
Preferred Qualifications:
- Prior experience on hardware design specifications and verification plan/matrix.
- Prior experience on RTL QA checks, including lint & CDC.
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Message to applicants applying to work in the U.S. and/or Canada:
The starting salary range posted for this position is $210,600.00 to $305,100.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.
U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:
- 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees.
- 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco.
- Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees.
- Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations).
- 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next.
- Additional paid time away may be requested to deal with critical or emergency issues for family members.
- Optional 10 paid days per full calendar year to volunteer.
For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:
- .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
- 1.5% of incentive target for each 1% of attainment between 50% and 75%;
- 1% of incentive target for each 1% of attainment between 75% and 100%; and
- Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.
The applicable full salary ranges for this position, by specific state, are listed below:
New York City Metro Area:
$210,600.00 - $350,800.00
Non-Metro New York state & Washington state:
$189,300.00 - $312,200.00
- For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.
Top Cities Hiring ASIC Design Engineers
Explore ASIC design engineer openings in the cities hiring most right now.
See All 281+ ASIC Design Engineer Jobs
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Find ASIC Design Engineer JobsASIC Design Engineer Job Market
Who's Hiring
- NVIDIA43
- Apple38
- Cisco14
- Google14
- Broadcom14
Top Industries Hiring
- Electronics & Hardware115
- Technology & Software101
- Artificial Intelligence23
- Law & Legal Services15
- Telecommunications12
What Employers Look For
The qualifications that appear most often in ASIC design engineer jobs.
- Bachelor's or master's degree in electrical engineering or computer engineering
- Proficiency in RTL design using Verilog or SystemVerilog
- Experience with synthesis and static timing analysis using Synopsys or Cadence tools
- Hands-on experience with digital verification methodologies including UVM or SystemVerilog assertions
- Familiarity with physical design flows including floorplanning, place and route, and signoff
- Experience taping out designs at a commercial foundry process node
Tips for Your ASIC Design Engineer Job Search
Tailor your resume to tape-out metrics
List specific tape-out milestones, process nodes you've worked on, and EDA tools by name. Hiring managers at fabless companies scan for Synopsys, Cadence, and Mentor tools explicitly, so generic mentions of 'design experience' won't surface your resume in their filters.
Apply early to roles that fit
Migrate Mate lists asic design engineer openings from across the United States in one place, so you can find roles that match and apply directly to each listing.
Target job postings by process node
Filter your search by node keywords like 5nm, 7nm, or 28nm when they appear in listings. Companies designing at advanced nodes often expect different toolchain fluency than those on mature processes, so matching your node experience to the posting gives your application a sharper angle.
Build a portfolio of RTL and synthesis results
Collect timing closure reports, area and power summaries, and block-level schematics you can discuss in technical interviews. Interviewers at ASIC-focused teams routinely ask candidates to walk through a design they owned from spec to signoff, so having concrete artifacts ready sets you apart.
Prepare for multi-stage technical interviews
Expect a coding or RTL coding screen, a logic design round covering FSMs and pipelines, and a system-level architecture discussion. Practice explaining design tradeoffs out loud, because interviewers assess how you reason through area-power-timing constraints, not just whether you arrive at the correct answer.
Negotiate based on node complexity and IP ownership
When you reach the offer stage, anchor your ask on the complexity of the IP you'll own and the node generation involved. Roles requiring full-chip integration at advanced nodes carry different scope than block-level work at mature nodes, and framing it that way in negotiation is defensible and specific.
ASIC Design Engineer Jobs: Frequently Asked Questions
Which companies are hiring the most asic design engineers?
NVIDIA, Apple, and Cisco are hiring the most asic design engineers right now, with openings concentrated in California, Texas, and Massachusetts, based on current listings on Migrate Mate as of June 2026. Semiconductor companies, cloud infrastructure teams building custom silicon, and automotive chipmakers are among the most active segments right now.
How many asic design engineer jobs are remote?
About 18% of asic design engineer openings are fully remote or hybrid as of June 2026, which is lower than in many software roles because lab access, EDA license servers, and tape-out collaboration often require on-site presence. Pre-silicon verification and architecture roles tend to offer the most remote flexibility within the field.
How do you become a asic design engineer?
Start with a bachelor's degree in electrical engineering or computer engineering with coursework in digital logic, VLSI design, and computer architecture. Build hands-on skills in RTL coding using Verilog or SystemVerilog through academic projects or open-source chip design efforts. Gain familiarity with industry EDA tools through university licenses or free academic tiers, then pursue internships or entry-level roles at semiconductor companies to get experience in a real tape-out flow.
Can you get hired as an asic design engineer with little or no experience?
Yes, entry-level asic design engineer roles exist, but employers expect you to demonstrate hands-on RTL work even without professional experience. Contributing to an open-source chip project, completing a VLSI course with a synthesizable design, or building a small FPGA prototype you can describe in depth all serve as substitutes for industry tape-out history when you're applying to new-grad or associate-level positions.
What does the asic design engineer interview process look like?
Most companies begin with a recruiter screen followed by a technical phone interview covering RTL coding, logic design fundamentals, and basic timing concepts. A virtual or on-site loop typically includes a coding round using Verilog or SystemVerilog, a design exercise where you're asked to architect a small block and discuss tradeoffs, and a system-level discussion with a senior engineer or architect. Some teams add a presentation where you walk through a past project in detail.
Where can I find and apply to asic design engineer jobs?
You can find and apply to asic design engineer jobs on Migrate Mate, which lists current openings from across the United States in one place. Search for roles that match your experience level, specialization, and preferred location, then apply directly to each listing that fits.
See All 281+ ASIC Design Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
Find ASIC Design Engineer Jobs