ASIC Design Engineer Jobs
ASIC Design Engineer jobs are open from new-grad to principal and staff levels across semiconductor companies, fabless chip design firms, and consumer electronics manufacturers, with specializations in RTL design, physical design, and verification. See the openings below and apply to the ones that match your experience.
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NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in an inclusive, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
We are now looking for a Senior ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded and datacenter platforms. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. Join our dynamic team today!
What you'll be doing:
- Understand the design and implementation, develop methodology and infrastructure to drive Performance, Power and Area (PPA) improvements.
- Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.
- Develop innovative memory subsystem designs to extend the state of the art performance and power efficiency. Collaborate with architects, designers, verification and VLSI teams to craft the industries' top performing GPUs.
What we need to see:
- BS Degree in CompE, EE, CS, or equivalent experience
- 5+ years of relevant industry experience
- Working knowledge of computer architecture fundamentals and their constructs in Verilog/System Verilog Strong interpersonal skills are required along with the ability to work in a diverse product oriented team.
Ways to stand out from the crowd:
- Strong analytical thought process and outstanding debug skills along with strong written and verbal communication skills to document methodologies, present power findings, and explain AI/ML‑based insights to both design and tools teams.
- Experience with caches, coherency, complex pipelines, arbiters, or interconnect networks
- Infrastructure development, use of AI to support design and verification development
- Familiarity with RTL implementation of low‑power techniques (e.g., clock gating, operand isolation, power gating strategies, multi‑VT usage) and their trade‑offs. Experience debugging RTL or gate‑level power anomalies by tracing logic cones, examining activity/toggle data, and identifying root‑cause structures or scenarios.
#LI-Hybrid
Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.
You will also be eligible for equity and benefits .
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in an inclusive, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
We are now looking for a Senior ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded and datacenter platforms. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. Join our dynamic team today!
What you'll be doing:
- Understand the design and implementation, develop methodology and infrastructure to drive Performance, Power and Area (PPA) improvements.
- Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.
- Develop innovative memory subsystem designs to extend the state of the art performance and power efficiency. Collaborate with architects, designers, verification and VLSI teams to craft the industries' top performing GPUs.
What we need to see:
- BS Degree in CompE, EE, CS, or equivalent experience
- 5+ years of relevant industry experience
- Working knowledge of computer architecture fundamentals and their constructs in Verilog/System Verilog Strong interpersonal skills are required along with the ability to work in a diverse product oriented team.
Ways to stand out from the crowd:
- Strong analytical thought process and outstanding debug skills along with strong written and verbal communication skills to document methodologies, present power findings, and explain AI/ML‑based insights to both design and tools teams.
- Experience with caches, coherency, complex pipelines, arbiters, or interconnect networks
- Infrastructure development, use of AI to support design and verification development
- Familiarity with RTL implementation of low‑power techniques (e.g., clock gating, operand isolation, power gating strategies, multi‑VT usage) and their trade‑offs. Experience debugging RTL or gate‑level power anomalies by tracing logic cones, examining activity/toggle data, and identifying root‑cause structures or scenarios.
#LI-Hybrid
Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.
You will also be eligible for equity and benefits .
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.ASIC Design Engineer Jobs by Experience Level
Top Cities Hiring ASIC Design Engineers
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Find ASIC Design Engineer JobsASIC Design Engineer Job Market
Who's Hiring
- Apple29
- Lockheed Martin21
- Qualcomm15
- Hewlett Packard Enterprise | HPE14
- Cisco13
Top Industries Hiring
- Technology & Software14
- Electronics & Hardware11
- Telecommunications7
- Media & Entertainment1
- Investment & Asset Management1
What Employers Look For
The qualifications that appear most often in ASIC design engineer jobs.
- Bachelor's or master's degree in electrical engineering or computer engineering
- Proficiency in RTL design using Verilog or SystemVerilog
- Experience with synthesis and static timing analysis using Synopsys or Cadence tools
- Hands-on experience with digital verification methodologies including UVM or SystemVerilog assertions
- Familiarity with physical design flows including floorplanning, place and route, and signoff
- Experience taping out designs at a commercial foundry process node
Tips for Your ASIC Design Engineer Job Search
Tailor your resume to tape-out metrics
List specific tape-out milestones, process nodes you've worked on, and EDA tools by name. Hiring managers at fabless companies scan for Synopsys, Cadence, and Mentor tools explicitly, so generic mentions of 'design experience' won't surface your resume in their filters.
Apply early to roles that fit
Migrate Mate lists asic design engineer openings from across the United States in one place, so you can find roles that match and apply directly to each listing.
Target job postings by process node
Filter your search by node keywords like 5nm, 7nm, or 28nm when they appear in listings. Companies designing at advanced nodes often expect different toolchain fluency than those on mature processes, so matching your node experience to the posting gives your application a sharper angle.
Build a portfolio of RTL and synthesis results
Collect timing closure reports, area and power summaries, and block-level schematics you can discuss in technical interviews. Interviewers at ASIC-focused teams routinely ask candidates to walk through a design they owned from spec to signoff, so having concrete artifacts ready sets you apart.
Prepare for multi-stage technical interviews
Expect a coding or RTL coding screen, a logic design round covering FSMs and pipelines, and a system-level architecture discussion. Practice explaining design tradeoffs out loud, because interviewers assess how you reason through area-power-timing constraints, not just whether you arrive at the correct answer.
Negotiate based on node complexity and IP ownership
When you reach the offer stage, anchor your ask on the complexity of the IP you'll own and the node generation involved. Roles requiring full-chip integration at advanced nodes carry different scope than block-level work at mature nodes, and framing it that way in negotiation is defensible and specific.
ASIC Design Engineer Jobs: Frequently Asked Questions
Which companies are hiring the most asic design engineers?
Apple, Lockheed Martin, and Qualcomm are hiring the most asic design engineers right now, with openings concentrated in California, Texas, and Colorado, based on current listings on Migrate Mate as of November 2026. Semiconductor companies, cloud infrastructure teams building custom silicon, and automotive chipmakers are among the most active segments right now.
How many asic design engineer jobs are remote?
About 45% of asic design engineer openings are fully remote or hybrid as of November 2026, which is lower than in many software roles because lab access, EDA license servers, and tape-out collaboration often require on-site presence. Pre-silicon verification and architecture roles tend to offer the most remote flexibility within the field.
How do you become a asic design engineer?
Start with a bachelor's degree in electrical engineering or computer engineering with coursework in digital logic, VLSI design, and computer architecture. Build hands-on skills in RTL coding using Verilog or SystemVerilog through academic projects or open-source chip design efforts. Gain familiarity with industry EDA tools through university licenses or free academic tiers, then pursue internships or entry-level roles at semiconductor companies to get experience in a real tape-out flow.
Can you get hired as an asic design engineer with little or no experience?
Yes, entry-level asic design engineer roles exist, but employers expect you to demonstrate hands-on RTL work even without professional experience. Contributing to an open-source chip project, completing a VLSI course with a synthesizable design, or building a small FPGA prototype you can describe in depth all serve as substitutes for industry tape-out history when you're applying to new-grad or associate-level positions.
What does the asic design engineer interview process look like?
Most companies begin with a recruiter screen followed by a technical phone interview covering RTL coding, logic design fundamentals, and basic timing concepts. A virtual or on-site loop typically includes a coding round using Verilog or SystemVerilog, a design exercise where you're asked to architect a small block and discuss tradeoffs, and a system-level discussion with a senior engineer or architect. Some teams add a presentation where you walk through a past project in detail.
Where can I find and apply to asic design engineer jobs?
You can find and apply to asic design engineer jobs on Migrate Mate, which lists current openings from across the United States in one place. Search for roles that match your experience level, specialization, and preferred location, then apply directly to each listing that fits.
See All 235+ ASIC Design Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
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