ASIC Design Engineer Jobs in Sunnyvale, CA
ASIC Design Engineer jobs in Sunnyvale, California are concentrated in the heart of Silicon Valley, with the strongest demand coming from semiconductor, consumer electronics, and wireless communications companies clustered around the downtown core, Peery Park, and the Lawrence Expressway corridor. Employers actively posting roles include Google, Meta, and Amazon. Scan the live roles below and apply to whichever ones fit.
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Showing 5 of 91+ ASIC Design Engineer jobs
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 12 years of experience in design verification.
- Experience in high-speed PHY layers, high-speed interface subsystems, or mixed-signal verification.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
- Experience defining verification architectures, methodologies, and roadmaps for AI accelerators, High-Performance Computing or high-bandwidth networking silicon.
- Experience bridging the gap between Pre-Silicon verification (simulation and emulation) and Post-Silicon validation and correlation.
- Experience driving advanced verification methodologies.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.As an ASIC Design Verification Technical Lead, you will define how Google verifies the physical-layer Digital Signal Processing (DSP) pipelines powering our next-generation AI hardware accelerators. You will drive the shift toward Emulation and Post-Silicon Correlation, ensuring that our architectural reference models and pre-silicon simulations perfectly match the physical behavior of the high-speed silicon in our planetary-scale AI data centers.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Design, build, and scale constrained-random verification environments using SystemVerilog and UVM for high-speed physical-layer DSP blocks.
- Build co-simulation frameworks and predictors to compare RTL implementation output against high-level algorithmic models.
- Define and execute functional coverage plans, utilizing covergroups and SystemVerilog Assertions to verify architectural corner cases, fixed-point quantization effects, and numerical overflows.
- Author dynamic stimulus sequences and virtual sequencers to stress-test adaptive feedback loops under realistic channel impairments, including noise, ISI, and high-frequency jitter profiles.
- Lead the debugging of RTL and environment failures, collaborating closely with algorithm and DSP designers to isolate and resolve discrepancies between the RTL implementation and the specification.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 12 years of experience in design verification.
- Experience in high-speed PHY layers, high-speed interface subsystems, or mixed-signal verification.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
- Experience defining verification architectures, methodologies, and roadmaps for AI accelerators, High-Performance Computing or high-bandwidth networking silicon.
- Experience bridging the gap between Pre-Silicon verification (simulation and emulation) and Post-Silicon validation and correlation.
- Experience driving advanced verification methodologies.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.As an ASIC Design Verification Technical Lead, you will define how Google verifies the physical-layer Digital Signal Processing (DSP) pipelines powering our next-generation AI hardware accelerators. You will drive the shift toward Emulation and Post-Silicon Correlation, ensuring that our architectural reference models and pre-silicon simulations perfectly match the physical behavior of the high-speed silicon in our planetary-scale AI data centers.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Design, build, and scale constrained-random verification environments using SystemVerilog and UVM for high-speed physical-layer DSP blocks.
- Build co-simulation frameworks and predictors to compare RTL implementation output against high-level algorithmic models.
- Define and execute functional coverage plans, utilizing covergroups and SystemVerilog Assertions to verify architectural corner cases, fixed-point quantization effects, and numerical overflows.
- Author dynamic stimulus sequences and virtual sequencers to stress-test adaptive feedback loops under realistic channel impairments, including noise, ISI, and high-frequency jitter profiles.
- Lead the debugging of RTL and environment failures, collaborating closely with algorithm and DSP designers to isolate and resolve discrepancies between the RTL implementation and the specification.
See All 91 ASIC Design Engineer Jobs in Sunnyvale
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Find ASIC Design Engineer JobsASIC Design Engineer Job Market in Sunnyvale
Who's Hiring
- Google34
- Meta15
- Amazon15
- Apple11
- Hewlett Packard Enterprise | HPE8
Top Industries Hiring
- Technology & Software27
- Artificial Intelligence15
- Retail8
- E-Commerce & Online Marketplaces8
- Manufacturing4
ASIC Design Engineer Jobs in Sunnyvale: Frequently Asked Questions
How do I get a asic design engineer job in Sunnyvale?
The strongest entry point in Sunnyvale is targeting semiconductor IP companies, fabless chip startups, and large consumer electronics firms concentrated along the Lawrence Expressway corridor and in Peery Park. Candidates with hands-on RTL design, timing closure, or physical design experience stand out most in this market. Familiarity with advanced process nodes below 7nm is a genuine differentiator, given the cutting-edge projects Sunnyvale employers typically run.
Which companies hire asic design engineers in Sunnyvale?
Sunnyvale asic design engineer roles are posted by Google, Meta, and Amazon and others right now, based on current listings on Migrate Mate as of August 2026. Sunnyvale's employer mix leans heavily toward fabless semiconductor companies, integrated device manufacturers, and large consumer electronics firms with in-house silicon design teams.
Are there remote asic design engineer jobs in Sunnyvale?
Remote opportunities are limited for asic design engineers because the role routinely requires lab access, chip bring-up, and direct collaboration with physical design and verification teams. About 27% of asic design engineer openings tied to Sunnyvale are remote or hybrid as of August 2026, and those tend to cover upstream RTL design or formal verification tasks that don't depend on on-site hardware.
How can I get a asic design engineer job in Sunnyvale with little or no experience?
The most realistic path in Sunnyvale is an ASIC verification or physical design intern role at one of the mid-size fabless companies clustered near Peery Park, which regularly recruit new graduates from nearby universities. Entry-level roles with titles like RTL design engineer or digital design verification engineer are the most common stepping stones locally. Proficiency in SystemVerilog and a demonstrable tapeout project, even from a university course, gives candidates a clear edge over general applicants.
Which industries hire the most asic design engineers in Sunnyvale?
Sunnyvale asic design engineer roles concentrate in Technology & Software, Artificial Intelligence, and Retail, based on current listings on Migrate Mate as of August 2026. Sunnyvale sits at the center of the global semiconductor supply chain, making it a natural hub for chip design talent across consumer, networking, and wireless applications.
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See All 91 ASIC Design Engineer Jobs in Sunnyvale
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