ASIC Design Engineer Jobs in California
ASIC Design Engineer jobs in California concentrate in Silicon Valley, San Diego, and the greater Los Angeles area, where semiconductor companies designing custom chips for mobile, automotive, and AI applications maintain their largest engineering teams. Qualcomm, Intel, and Apple are among the most established employers, each running dedicated RTL-to-GDSII teams that hire across a full range of seniority, from junior verification engineers to principal design leads. Physical design, digital verification, and low-power architecture are the specialties that appear most consistently in California postings. See the openings below and apply to the ones that match your experience.
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Showing 5 of 96+ ASIC Design Engineer jobs
About Eridu
Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today’s AI performance is frequently limited by communication bottlenecks. Eridu delivers multiple industry-first innovations across silicon, packaging, software, and systems to deliver a step function in AI networking – a network switch that is an order of magnitude improvement in bandwidth and radix versus today’s “state of the art” switches. This is the first silicon and system designed from the ground up for AI and the increase in radix and throughput unlocks greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs, improving reliability, simplifying operations and speeding AI data center deployments for faster time to revenue.
The company’s solutions and value proposition have been widely validated by leading hyperscalers.
The company has raised $200M to date including its most recent, oversubscribed Series A round led by Socratic Partners, John Doerr, Hudson River Trading, Capricorn Investment Group and Matter Venture Partners, with participation by SBVA, MediaTek, Bosch Ventures, TDK Ventures, Eclipse Ventures, and VentureTech Alliance, among others.
Eridu is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exists, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu has also assembled a world class IP, design and manufacturing ecosystem to execute on its vision, and counts TSMC as a key partner in our journey.
Visit our website eridu.ai to learn more.
Position Overview
We are seeking a hands-on ASIC Design Verification Lead to own verification execution for complex, high-performance networking silicon. This role is a senior technical leadership position focused on driving verification strategy, infrastructure, and closure, while remaining deeply involved in day-to-day hands-on verification work.
This is not a people-manager-only role. The ideal candidate is a highly technical verification leader who has personally taken chips to tape-out, understands how verification breaks late in the cycle, and can drive functional correctness, coverage closure, and tape-out readiness in a fast-moving startup environment.
Responsibilities
Verification Strategy & Execution
- Define and own block-, subsystem-, and chip-level verification strategies
- Develop and maintain scalable verification environments using SystemVerilog and UVM
- Drive execution from test-plan definition through coverage and bug closure
- Ensure verification readiness as a gating requirement for tape-out
Hands-on Verification Development
- Write and review high-quality testbenches, sequences, checkers, and scoreboards
- Develop constrained-random, directed, and stress tests to validate complex corner cases
- Actively debug functional failures across RTL, testbench, and simulation environments
Coverage & Quality Ownership
- Define functional, code, and assertion coverage goals
- Analyze coverage results and identify verification gaps
- Provide clear, actionable feedback to RTL designers to improve design and test quality
Cross-Functional Debug & Collaboration
- Partner closely with RTL, architecture, physical design, and firmware teams
- Drive root-cause analysis of functional, performance, and integration issues
- Support gate-level, timing-aware, and power-aware simulations as required
- Partner and support emulation and post silicon validation of the ASIC design
Full-Chip & Pre-Silicon Validation
- Lead full-chip verification planning, execution, and closure
- Support emulation and acceleration environments where appropriate
- Ensure clean handoff to silicon bring-up teams with high confidence in design correctness
Execution Discipline & Technical Leadership
- Establish and enforce verification checklists and quality gates
- Track verification progress and risk, proactively escalating issues
- Lead by technical authority and hands-on contribution rather than coordination alone
- Continuously improve verification methodology, infrastructure, and best practices
Qualifications
- Strong hands-on experience in ASIC design verification
- Proven track record of taking at least one complex ASIC to tape-out with direct verification ownership
- Deep expertise in SystemVerilog and UVM-based verification methodologies
- Strong understanding of ASIC design and verification flows, including simulation, coverage, and debug
- Experience with block-level through full-chip verification and integration
- Ability to drive execution in ambiguous, fast-paced startup environments
- Excellent communication skills and ability to collaborate across disciplines
Nice to Have
- Networking ASIC verification experience (Ethernet-based systems preferred)
- Experience with gate-level, timing-aware, and low-power verification
- Familiarity with high-speed interfaces and chip-to-chip interconnects
- Experience with emulation, acceleration, or FPGA-based validation
- Post-silicon debug experience and RTL-to-silicon correlation
Why Join Us?
At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.
The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
Notice to Recruiting Agencies
Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.
About Eridu
Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today’s AI performance is frequently limited by communication bottlenecks. Eridu delivers multiple industry-first innovations across silicon, packaging, software, and systems to deliver a step function in AI networking – a network switch that is an order of magnitude improvement in bandwidth and radix versus today’s “state of the art” switches. This is the first silicon and system designed from the ground up for AI and the increase in radix and throughput unlocks greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs, improving reliability, simplifying operations and speeding AI data center deployments for faster time to revenue.
The company’s solutions and value proposition have been widely validated by leading hyperscalers.
The company has raised $200M to date including its most recent, oversubscribed Series A round led by Socratic Partners, John Doerr, Hudson River Trading, Capricorn Investment Group and Matter Venture Partners, with participation by SBVA, MediaTek, Bosch Ventures, TDK Ventures, Eclipse Ventures, and VentureTech Alliance, among others.
Eridu is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exists, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu has also assembled a world class IP, design and manufacturing ecosystem to execute on its vision, and counts TSMC as a key partner in our journey.
Visit our website eridu.ai to learn more.
Position Overview
We are seeking a hands-on ASIC Design Verification Lead to own verification execution for complex, high-performance networking silicon. This role is a senior technical leadership position focused on driving verification strategy, infrastructure, and closure, while remaining deeply involved in day-to-day hands-on verification work.
This is not a people-manager-only role. The ideal candidate is a highly technical verification leader who has personally taken chips to tape-out, understands how verification breaks late in the cycle, and can drive functional correctness, coverage closure, and tape-out readiness in a fast-moving startup environment.
Responsibilities
Verification Strategy & Execution
- Define and own block-, subsystem-, and chip-level verification strategies
- Develop and maintain scalable verification environments using SystemVerilog and UVM
- Drive execution from test-plan definition through coverage and bug closure
- Ensure verification readiness as a gating requirement for tape-out
Hands-on Verification Development
- Write and review high-quality testbenches, sequences, checkers, and scoreboards
- Develop constrained-random, directed, and stress tests to validate complex corner cases
- Actively debug functional failures across RTL, testbench, and simulation environments
Coverage & Quality Ownership
- Define functional, code, and assertion coverage goals
- Analyze coverage results and identify verification gaps
- Provide clear, actionable feedback to RTL designers to improve design and test quality
Cross-Functional Debug & Collaboration
- Partner closely with RTL, architecture, physical design, and firmware teams
- Drive root-cause analysis of functional, performance, and integration issues
- Support gate-level, timing-aware, and power-aware simulations as required
- Partner and support emulation and post silicon validation of the ASIC design
Full-Chip & Pre-Silicon Validation
- Lead full-chip verification planning, execution, and closure
- Support emulation and acceleration environments where appropriate
- Ensure clean handoff to silicon bring-up teams with high confidence in design correctness
Execution Discipline & Technical Leadership
- Establish and enforce verification checklists and quality gates
- Track verification progress and risk, proactively escalating issues
- Lead by technical authority and hands-on contribution rather than coordination alone
- Continuously improve verification methodology, infrastructure, and best practices
Qualifications
- Strong hands-on experience in ASIC design verification
- Proven track record of taking at least one complex ASIC to tape-out with direct verification ownership
- Deep expertise in SystemVerilog and UVM-based verification methodologies
- Strong understanding of ASIC design and verification flows, including simulation, coverage, and debug
- Experience with block-level through full-chip verification and integration
- Ability to drive execution in ambiguous, fast-paced startup environments
- Excellent communication skills and ability to collaborate across disciplines
Nice to Have
- Networking ASIC verification experience (Ethernet-based systems preferred)
- Experience with gate-level, timing-aware, and low-power verification
- Familiarity with high-speed interfaces and chip-to-chip interconnects
- Experience with emulation, acceleration, or FPGA-based validation
- Post-silicon debug experience and RTL-to-silicon correlation
Why Join Us?
At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.
The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
Notice to Recruiting Agencies
Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.
See All 96 ASIC Design Engineer Jobs in California
Find roles in California that match your experience and apply in just a few clicks.
Find ASIC Design Engineer JobsASIC Design Engineer Jobs by City in California
Where California roles are concentrated, by current openings.
ASIC Design Engineer Job Market in California
A snapshot from current California openings, updated as new roles post.
Who's Hiring
- Apple11
- Google11
- Qualcomm9
- Cisco6
- Meta5
Top Industries Hiring
- Technology & Software
- Electronics & Hardware
- Banking & Financial Services
- Telecommunications
- Law & Legal Services
What California Employers Look For
The qualifications that appear most often in ASIC design engineer jobs across California.
- Bachelor's or master's degree in electrical engineering or computer engineering required
- Hands-on RTL design and synthesis experience using Verilog or SystemVerilog
- Proficiency with industry EDA tools such as Synopsys Design Compiler or Cadence Innovus
- Experience with functional verification methodologies including UVM or constrained-random simulation
- Familiarity with timing closure, static timing analysis, and physical implementation flows
- Strong understanding of low-power design techniques including clock gating and power domains
ASIC Design Engineer Jobs in California: Frequently Asked Questions
How do you become a asic design engineer in California?
Most asic design engineers in California enter the field with a bachelor's or master's degree in electrical engineering or computer engineering, and California employers typically treat the master's degree as a strong differentiator for RTL and physical design roles. There is no state-issued license required to work as an asic design engineer in California. Candidates build their qualifications through university coursework in digital design, internships at semiconductor companies, and hands-on EDA tool experience before applying to full-time openings.
Which companies hire asic design engineers in California?
Employers hiring asic design engineers in California right now include Apple, Google, and Qualcomm, based on current listings on Migrate Mate as of September 2026. California's deep semiconductor ecosystem, anchored by decades of chip design activity in Silicon Valley and San Diego, means the employer list extends well beyond a handful of names and includes fabless startups, established systems companies, and automotive semiconductor divisions.
Which California cities have the most asic design engineer jobs?
Sunnyvale, San Jose, and Santa Clara account for the largest share of asic design engineer openings in California. Silicon Valley's concentration of fabless semiconductor companies and large systems firms drives the dominant share of demand, while San Diego is home to Qualcomm's headquarters and a dense cluster of wireless and mobile chip teams, and Los Angeles reflects growing activity in automotive and AI chip design.
Are there remote asic design engineer jobs in California?
Yes, but they're rare. ASIC design work is heavily lab- and tool-dependent, and most California employers expect engineers on-site for tape-out cycles, silicon bring-up, and EDA server access. About 33% of asic design engineer openings tied to California are remote or hybrid as of September 2026, and those postings tend to cover architecture, micro-architecture review, or RTL specification work that does not require direct lab access.
How can I get hired as a asic design engineer in California with little or no experience?
The most realistic entry path is a master's program with a strong digital design or VLSI focus at a California university, which routinely feeds directly into new-grad hiring pipelines at companies like Qualcomm, Apple, and Intel through on-campus recruiting. Many large California semiconductor employers run structured new-grad rotational programs that place candidates in RTL design, verification, or physical design teams. Adjacent roles such as FPGA engineer, design verification engineer, or EDA applications engineer at a California tool vendor also serve as common lateral entries into full ASIC design positions.
Where can I find and apply to asic design engineer jobs in California?
You can find and apply to asic design engineer jobs in California on Migrate Mate, which lists current California openings. Search the roles that fit your background, review the requirements, and apply directly to the ones that match your experience and target location.
See All 96 ASIC Design Engineer Jobs in California
Find roles in California that match your experience and apply in just a few clicks.
Find ASIC Design Engineer Jobs