ASIC Design Engineer Jobs in California
ASIC Design Engineer jobs in California concentrate in Silicon Valley, San Diego, and the greater Los Angeles area, where semiconductor companies designing custom chips for mobile, automotive, and AI applications maintain their largest engineering teams. Qualcomm, Intel, and Apple are among the most established employers, each running dedicated RTL-to-GDSII teams that hire across a full range of seniority, from junior verification engineers to principal design leads. Physical design, digital verification, and low-power architecture are the specialties that appear most consistently in California postings. See the openings below and apply to the ones that match your experience.
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Showing 5 of 137+ ASIC Design Engineer jobs
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in an inclusive, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
We are now looking for a Senior ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded and datacenter platforms. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. Join our dynamic team today!
What you'll be doing:
- Understand the design and implementation, develop methodology and infrastructure to drive Performance, Power and Area (PPA) improvements.
- Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.
- Develop innovative memory subsystem designs to extend the state of the art performance and power efficiency. Collaborate with architects, designers, verification and VLSI teams to craft the industries' top performing GPUs.
What we need to see:
- BS Degree in CompE, EE, CS, or equivalent experience
- 5+ years of relevant industry experience
- Working knowledge of computer architecture fundamentals and their constructs in Verilog/System Verilog Strong interpersonal skills are required along with the ability to work in a diverse product oriented team.
Ways to stand out from the crowd:
- Strong analytical thought process and outstanding debug skills along with strong written and verbal communication skills to document methodologies, present power findings, and explain AI/ML‑based insights to both design and tools teams.
- Experience with caches, coherency, complex pipelines, arbiters, or interconnect networks
- Infrastructure development, use of AI to support design and verification development
- Familiarity with RTL implementation of low‑power techniques (e.g., clock gating, operand isolation, power gating strategies, multi‑VT usage) and their trade‑offs. Experience debugging RTL or gate‑level power anomalies by tracing logic cones, examining activity/toggle data, and identifying root‑cause structures or scenarios.
#LI-Hybrid
Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.
You will also be eligible for equity and benefits .
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in an inclusive, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
We are now looking for a Senior ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded and datacenter platforms. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. Join our dynamic team today!
What you'll be doing:
- Understand the design and implementation, develop methodology and infrastructure to drive Performance, Power and Area (PPA) improvements.
- Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.
- Develop innovative memory subsystem designs to extend the state of the art performance and power efficiency. Collaborate with architects, designers, verification and VLSI teams to craft the industries' top performing GPUs.
What we need to see:
- BS Degree in CompE, EE, CS, or equivalent experience
- 5+ years of relevant industry experience
- Working knowledge of computer architecture fundamentals and their constructs in Verilog/System Verilog Strong interpersonal skills are required along with the ability to work in a diverse product oriented team.
Ways to stand out from the crowd:
- Strong analytical thought process and outstanding debug skills along with strong written and verbal communication skills to document methodologies, present power findings, and explain AI/ML‑based insights to both design and tools teams.
- Experience with caches, coherency, complex pipelines, arbiters, or interconnect networks
- Infrastructure development, use of AI to support design and verification development
- Familiarity with RTL implementation of low‑power techniques (e.g., clock gating, operand isolation, power gating strategies, multi‑VT usage) and their trade‑offs. Experience debugging RTL or gate‑level power anomalies by tracing logic cones, examining activity/toggle data, and identifying root‑cause structures or scenarios.
#LI-Hybrid
Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.
You will also be eligible for equity and benefits .
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.See All 137+ ASIC Design Engineer Jobs in California
Find roles in California that match your experience and apply in just a few clicks.
Find ASIC Design Engineer JobsASIC Design Engineer Jobs by City in California
Where California roles are concentrated, by current openings.
ASIC Design Engineer Job Market in California
A snapshot from current California openings, updated as new roles post.
Who's Hiring
- Apple21
- Qualcomm15
- Cisco13
- Google11
- NVIDIA11
Top Industries Hiring
- Technology & Software11
- Electronics & Hardware8
- Telecommunications7
- Media & Entertainment1
What California Employers Look For
The qualifications that appear most often in ASIC design engineer jobs across California.
- Bachelor's or master's degree in electrical engineering or computer engineering required
- Hands-on RTL design and synthesis experience using Verilog or SystemVerilog
- Proficiency with industry EDA tools such as Synopsys Design Compiler or Cadence Innovus
- Experience with functional verification methodologies including UVM or constrained-random simulation
- Familiarity with timing closure, static timing analysis, and physical implementation flows
- Strong understanding of low-power design techniques including clock gating and power domains
ASIC Design Engineer Jobs in California: Frequently Asked Questions
How do you become a asic design engineer in California?
Most asic design engineers in California enter the field with a bachelor's or master's degree in electrical engineering or computer engineering, and California employers typically treat the master's degree as a strong differentiator for RTL and physical design roles. There is no state-issued license required to work as an asic design engineer in California. Candidates build their qualifications through university coursework in digital design, internships at semiconductor companies, and hands-on EDA tool experience before applying to full-time openings.
Which companies hire asic design engineers in California?
Employers hiring asic design engineers in California right now include Apple, Qualcomm, and Cisco, based on current listings on Migrate Mate as of November 2026. California's deep semiconductor ecosystem, anchored by decades of chip design activity in Silicon Valley and San Diego, means the employer list extends well beyond a handful of names and includes fabless startups, established systems companies, and automotive semiconductor divisions.
Which California cities have the most asic design engineer jobs?
Sunnyvale, San Jose, and Santa Clara account for the largest share of asic design engineer openings in California. Silicon Valley's concentration of fabless semiconductor companies and large systems firms drives the dominant share of demand, while San Diego is home to Qualcomm's headquarters and a dense cluster of wireless and mobile chip teams, and Los Angeles reflects growing activity in automotive and AI chip design.
Are there remote asic design engineer jobs in California?
Yes, but they're rare. ASIC design work is heavily lab- and tool-dependent, and most California employers expect engineers on-site for tape-out cycles, silicon bring-up, and EDA server access. About 49% of asic design engineer openings tied to California are remote or hybrid as of November 2026, and those postings tend to cover architecture, micro-architecture review, or RTL specification work that does not require direct lab access.
How can I get hired as a asic design engineer in California with little or no experience?
The most realistic entry path is a master's program with a strong digital design or VLSI focus at a California university, which routinely feeds directly into new-grad hiring pipelines at companies like Qualcomm, Apple, and Intel through on-campus recruiting. Many large California semiconductor employers run structured new-grad rotational programs that place candidates in RTL design, verification, or physical design teams. Adjacent roles such as FPGA engineer, design verification engineer, or EDA applications engineer at a California tool vendor also serve as common lateral entries into full ASIC design positions.
Where can I find and apply to asic design engineer jobs in California?
You can find and apply to asic design engineer jobs in California on Migrate Mate, which lists current California openings. Search the roles that fit your background, review the requirements, and apply directly to the ones that match your experience and target location.
See All 137+ ASIC Design Engineer Jobs in California
Find roles in California that match your experience and apply in just a few clicks.
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