ASIC Design Engineer Jobs in California
ASIC Design Engineer jobs in California are in active demand across San Jose, Santa Clara, and Sunnyvale and other California metros, including employers like Apple, Cisco, and NVIDIA. See the openings below and apply to the ones that match your experience.
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The application window is expected to close on: 08/01/2026. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Meet the Team
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Your Impact
- RTL-to-GDSII implementation, including Logic Synthesis, Hierarchical Floorplanning, Place and Route, Static Timing Analysis, Power Integrity, and Equivalence checks with a focus on Power, Performance and Die-Size Optimization.
- Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.
- Work closely with RTL, DFT, Implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology.
- Guide Clock Tree Synthesis (CTS) strategies and provide actionable feedback to the implementation teams.
- Execute STA setup, convergence methodologies, and sign-off processes across multi-mode, multi-corner scenarios.
- Complete Functional and Timing ECO implementation using industry-standard flows and contribute to automation for STA methodology.
- Evaluate multiple timing methodologies/tools across different technologies and design types.
Minimum Qualifications
- Bachelor’s degree in Engineering and 15+ years of ASIC related experience, Master’s degree in Engineering and 12+ years of ASIC related experience, or PhD in Engineering and 7+ years of ASIC related experience.
- Experience developing and driving methodologies in the area of Power Optimization and Analysis.
- Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies.
- Experience working with EDA tools like Innovus, Primetime/Tempus, Redhawk/Voltus and Calibre.
Preferred Qualifications
- Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis.
- Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
- Experience in Fullchip floor-planning and power grid planning.
- Experience with custom clock (H-Tree or Mesh) at chip level.
- Experience with Python, TCL, or Perl programming.
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Message to applicants applying to work in the U.S. and/or Canada:
The starting salary range posted for this position is $231,400.00 to $331,800.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.
U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:
- 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
- Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
- Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
- 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:
- .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
- 1.5% of incentive target for each 1% of attainment between 50% and 75%;
- 1% of incentive target for each 1% of attainment between 75% and 100%; and
- Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.
The applicable full salary ranges for this position, by specific state, are listed below:
New York City Metro Area:
$231,400.00 - $381,600.00
Non-Metro New York state & Washington state:
$222,900.00 - $343,600.00
- For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.
See All 170+ ASIC Design Engineer Jobs in California
Find roles in California that match your experience and apply in just a few clicks.
Find ASIC Design Engineer JobsASIC Design Engineer Jobs by City in California
Where California roles are concentrated, by current openings.
ASIC Design Engineer Job Market in California
A snapshot from current California openings, updated as new roles post.
Who's Hiring
- Apple24

- Cisco17

- NVIDIA15

- Google14

- Broadcom10

Top Industries Hiring
- Electronics & Hardware79
- Technology & Software67
- Artificial Intelligence18
- Telecommunications12
- Aerospace & Defense7
What California Employers Look For
The qualifications that appear most often in ASIC design engineer jobs across California.
- Bachelor's or master's degree in electrical engineering or computer engineering
- Proficiency in RTL design using Verilog or SystemVerilog
- Experience with synthesis and static timing analysis using Synopsys or Cadence tools
- Hands-on experience with digital verification methodologies including UVM or SystemVerilog assertions
- Familiarity with physical design flows including floorplanning, place and route, and signoff
- Experience taping out designs at a commercial foundry process node
ASIC Design Engineer Jobs in California: Frequently Asked Questions
How many ASIC design engineer jobs are there in California?
There are 170+ ASIC design engineer openings in California on Migrate Mate as of June 2026, with the most roles in San Jose, Santa Clara, and Sunnyvale. New positions post regularly as employers across California hire.
Which California cities have the most ASIC design engineer jobs?
San Jose, Santa Clara, and Sunnyvale have the most ASIC design engineer openings in California right now, with additional roles spread across smaller metros statewide.
Which companies hire ASIC design engineers in California?
Employers hiring ASIC design engineers in California include Apple, Cisco, and NVIDIA, based on current listings on Migrate Mate as of June 2026.
Are there remote ASIC design engineer jobs in California?
Yes. About 10% of ASIC design engineer openings tied to California are remote or hybrid as of June 2026. The rest are on-site roles based in California metros.
How do I apply for ASIC design engineer jobs in California?
You can apply to ASIC design engineer jobs in California directly on Migrate Mate. Search the listings above, find roles that match your experience and preferred California location, then apply to each one that fits.
See All 170+ ASIC Design Engineer Jobs in California
Find roles in California that match your experience and apply in just a few clicks.
Find ASIC Design Engineer Jobs