Remote Senior Physical Design Engineer Jobs
Remote Senior Physical Design Engineer jobs are open across the U.S. at remote-first semiconductor and hardware firms, distributed chip design teams, and fabless companies with engineering headcount spread across multiple time zones. Employers hiring remotely right now include Positron AI, WSB, and Olsson. Scan the live roles below and apply to whichever ones fit.
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K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.
The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.
With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.
The Role
We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow—from synthesis to GDSII—working closely with architecture, RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space.
Responsibilities
- Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification.
- Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
- Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence.
- Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment.
- Develop and maintain scripts and automation to improve flow efficiency and consistency.
- Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis.
- Assist in chip-level integration, ECOs, and tapeout preparation.
- Contribute to methodology development, tool evaluation, and flow documentation.
- Support your product through production and spaceflight.
Required Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
- 5–10 years of experience in ASIC physical design for complex SoCs.
- Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent).
- Strong understanding of timing analysis, power optimization, and physical verification flows.
- Experience with hierarchical or flat SoC design methodologies.
- Familiarity with FinFET technologies.
- Working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
- Strong problem-solving skills and ability to work cross-functionally in fast-paced environments.
Preferred Qualifications
- Exposure to radiation-hardened or space-qualified ASICs.
- Experience with chip-package co-design or advanced packaging (2.5D/3D).
- Familiarity with physical design service vendor management or offshore collaboration.
- Experience with sign-off through TSMC.
- Experience with Gate-All-Around technologies.
- Experience working in cross-functional, geographically distributed teams.
Compensation and Benefits:
- Base salary range for this role is $170,000 – $250,000 + equity in the company
- Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
- Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!
If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.
Export Compliance
As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."
The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
Equal Opportunity
K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.
The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.
With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.
The Role
We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow—from synthesis to GDSII—working closely with architecture, RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space.
Responsibilities
- Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification.
- Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
- Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence.
- Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment.
- Develop and maintain scripts and automation to improve flow efficiency and consistency.
- Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis.
- Assist in chip-level integration, ECOs, and tapeout preparation.
- Contribute to methodology development, tool evaluation, and flow documentation.
- Support your product through production and spaceflight.
Required Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
- 5–10 years of experience in ASIC physical design for complex SoCs.
- Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent).
- Strong understanding of timing analysis, power optimization, and physical verification flows.
- Experience with hierarchical or flat SoC design methodologies.
- Familiarity with FinFET technologies.
- Working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
- Strong problem-solving skills and ability to work cross-functionally in fast-paced environments.
Preferred Qualifications
- Exposure to radiation-hardened or space-qualified ASICs.
- Experience with chip-package co-design or advanced packaging (2.5D/3D).
- Familiarity with physical design service vendor management or offshore collaboration.
- Experience with sign-off through TSMC.
- Experience with Gate-All-Around technologies.
- Experience working in cross-functional, geographically distributed teams.
Compensation and Benefits:
- Base salary range for this role is $170,000 – $250,000 + equity in the company
- Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
- Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!
If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.
Export Compliance
As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."
The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
Equal Opportunity
K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
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Find JobsRemote Senior Physical Design Engineer Job Market
Who's Hiring
Top Industries Hiring
- Consulting & Professional Services
What Employers Look For
The qualifications that appear most often in remote senior physical design engineer jobs.
- 5+ years of experience in physical design at advanced process nodes
- Proficiency in Cadence Innovus or Synopsys IC Compiler for full-flow implementation
- Hands-on experience with floorplanning, placement, routing, and timing closure
- Strong understanding of static timing analysis using PrimeTime or similar tools
- Bachelor's or master's degree in electrical engineering, computer engineering, or a related field
- Experience with DRC and LVS signoff using Mentor Calibre or equivalent verification tools
Tips for Your Remote Senior Physical Design Engineer Job Search
Apply early to remote roles that fit
Migrate Mate lists remote senior physical design engineer openings from across the U.S. in one place. Search the current listings, identify roles that match your process node experience and EDA tool stack, and apply directly before competitive openings fill.
Show tape-out ownership in your resume
Remote physical design teams need engineers who can own a block from floorplan through signoff without daily check-ins. List the nodes, block sizes, and tape-out outcomes you delivered to give hiring managers a concrete picture of your independent execution capability.
Demonstrate async communication before the interview
Distributed semiconductor teams screen heavily for written clarity. Your cover note and any pre-screen responses should be precise and structured, since remote physical design coordination happens through Jira, Confluence, and email more than in-person whiteboard sessions.
Prepare your remote EDA setup discussion
Remote physical design interviews often include questions about how you manage tool licenses, run jobs on remote compute clusters, and handle PDK access securely outside a lab. Know your preferred EDA environment and be ready to explain your remote workflow concretely.
Remote Senior Physical Design Engineer Jobs: Frequently Asked Questions
How do I get a remote senior physical design engineer job?
Remote senior physical design engineer roles go to candidates who can demonstrate deep IC layout expertise, strong floorplanning and timing closure skills, and the discipline to execute complex physical design tasks without on-site oversight. Fabless startups and distributed semiconductor teams hire remotely most actively. What sets candidates apart is a clear portfolio of tape-outs, fluency with industry-standard EDA tools, and the ability to communicate progress clearly in writing through Slack, Confluence, or similar async channels.
Which companies hire remote senior physical design engineers?
Companies hiring remote senior physical design engineers right now include Positron AI, WSB, and Olsson, based on current remote listings on Migrate Mate as of November 2026. These tend to be fabless semiconductor firms, IP licensing companies, and hardware-focused startups that have built distributed engineering teams and are comfortable managing complex physical design workflows across time zones.
Can you get a remote senior physical design engineer job with no experience?
Yes, but remote entry-level physical design roles are uncommon because the work requires independent judgment on complex floorplanning, power, and timing tradeoffs with minimal real-time mentorship. Candidates who break in remotely typically show tapeout contributions from academic or open-source projects, strong EDA tool proficiency demonstrated through coursework, and clear written communication skills that signal they can function effectively on a distributed team.
Do you need a degree for remote senior physical design engineer jobs?
Usually, but a bachelor's or master's degree in electrical engineering, computer engineering, or a related field is the common baseline rather than a hard requirement at every employer. Remote hiring managers weigh hands-on tapeout experience, demonstrated proficiency in tools like Cadence Innovus or Synopsys ICC2, and a record of delivering signoff-quality results more heavily than the credential alone when evaluating senior candidates.
Which industries hire the most remote senior physical design engineers?
Most remote senior physical design engineer openings sit in Consulting & Professional Services, per current remote listings on Migrate Mate as of November 2026. These sectors rely on distributed chip design teams where physical design engineers can collaborate effectively across time zones using shared EDA environments and async communication tools.
See All 9 Remote Senior Physical Design Engineer Jobs
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