Test Engineer Jobs in Boston, MA

INTRODUCTION

We are building terahertz imaging radar for automotive perception. Our sensor architecture combines millimeter-wave transmit and receive front-ends, a high-channel-count data conversion front-end, and an integrated radar signal processor. These are automotive parts headed for AEC-Q qualification and volume production with Tier 1 customers.

THE ROLE

Our next-generation sensor SoC is a multi-chip module that co-packages a high-channel-count mixed-signal data conversion die with a digital compute die carrying a real-time processor, DSP cluster with FFT acceleration, GPU, functional safety monitor, hardware security module, external DRAM interface, and automotive Ethernet. The two dies communicate over a high-speed die-to-die link across a fine-pitch, automotive-grade interposer. We are looking for an engineer who will own the product test for this module. You will define and drive wafer probe and final test for both dies and for the integrated package - building the test programs, owning the test hardware, and managing our contract manufacturers, OSATs, and test houses to get from first silicon to qualified, yielding, production-tested parts. This is a hands-on role with real scope: you set the test strategy, you sit at the prober during bring-up, and you own the AEC-Q campaign that makes the part shippable.

Responsibilities

First-silicon bring-up

- Lead bench and ATE bring-up of both the die and the co-packaged module as parts return from fab and assembly.
- Own the wafer probe and ATE plan for the module, from strategy through execution.
- Debug first-silicon issues alongside design, DFT, and package teams; drive failures to root cause across analog, digital, and interconnect domains.
- Bring up the die-to-die link at test: link training, sideband channel behavior, BER and margining, and the known-good-die criteria that gate assembly.

Wafer probe (sort)

- Define wafer sort flows and test coverage for both a mixed-signal data conversion die and a digital compute die - two very different test problems on the same program.
- Specify and qualify probe cards with leading probe card suppliers; own pinout sign-off against the bump map, first-article inspection, and probe-mark and contact-resistance qualification.
- Build known-good-die screening rigorous enough to protect module assembly yield, including per-die traceability, OTP/eFuse programming for device ID and wafer coordinates, and calibration data write.
- Set up wafer map handling, bin definitions, and yield reporting from the sort floor.

Final test and ATE program development

- Develop and own production ATE test programs covering IDDQ, functional, scan (stuck-at and at-speed), MBIST, DC parametrics (VOH/VOL, IOH/IOL, ZOH/ZOL), serial interface timing, static and dynamic current, PLL and clocking, and temperature sensor trim and calibration.
- Own analog and mixed-signal test methodology for the data conversion path: ENOB, SNR/SNDR, INL/DNL, offset and gain trim, channel-to-channel matching and crosstalk, and converter test modes.
- Translate designer-supplied simulation collateral and DFT deliverables into production patterns; close the loop with design and DFT on testability gaps before tapeout, not after.
- Design and bring up load boards and characterization boards; drive socket selection and qualification with package and socket vendors, including thermal and contact-life considerations at automotive temperature extremes.
- Own full PVT characterization across corners, bench-to-ATE correlation, Gage R&R, and datasheet limit derivation - you turn characterization data into guardbanded production limits.

Working with contract manufacturers and test partners

- Serve as the primary technical interface to our external test partners for hardware and program bring-up, program transfer, and production ramp.
- Write and manage test statements of work, review vendor quotes and schedules, and hold partners to committed deliverables.
- Drive local-to-offshore test correlation and site-to-site matching as programs move from a development test house to the fab’s production floor; own the correlation and Gage R&R data that justifies the transfer.
- Manage multi-site conversion decisions against volume forecasts and test cost targets.

AEC-Q qualification

- Own the AEC-Q100 and AEC-Q104 test plan for the module. AEC-Q104 governs multi-chip modules and advanced packages, and module qualification is materially harder than single-die - you will be the person who knows why.
- Define and execute the qualification flow: HTOL, temperature cycling, HAST/THB, preconditioning, ESD (AEC-Q100-002 HBM, -011 CDM), latch-up, and early life failure screening.
- Specify and bring up qualification hardware - schematic and PCB for burn-in and HTOL boards - and drive it through partners offering turnkey qualification and burn-in support.
- Interface with reliability, package engineering, and functional safety on package-level failure mechanisms: warpage across a dense interposer, solder crack detection structures, thermal gradients, and on-package sensing features designed for test.
- Support customer and Tier 1 qualification reviews, PPAP traceability, and 8D failure analysis response.

Production

- Own yield monitoring, test time reduction, test cost per unit, and yield improvement once parts are in production.
- Build the outlier screening and part average testing (PAT/SPAT) discipline automotive customers expect.

REQUIREMENTS

- Degree in Electrical Engineering or equivalent, with 8-15+ years in product or test engineering for production silicon.
- Demonstrated ownership of a device from first silicon through wafer sort, final test, and volume production - at least one full cycle, start to finish.
- Deep hands-on experience on production ATE platforms, including test program architecture and debug, not just execution.
- Both analog/mixed-signal and digital test experience. Data converter characterization and trim on one side; scan, MBIST, IDDQ, and DFT-based digital test on the other. This role needs both because the module contains both.
- Strong wafer probe background: probe card specification and qualification, prober setup, contact and probe mark issues, wafer map and bin management.
- Proven track record managing OSATs, contract manufacturers, and test houses as an engineering counterpart - driving schedules, reviewing hardware designs, and resolving technical disputes.
- Direct experience taking parts through AEC-Q100 qualification, including test plan authorship and qualification hardware definition.
- Load board and characterization board design experience; comfortable reading schematics and working with layout engineers on high-speed, high-pin-count test hardware.
- Fluency in test data analysis and in the statistics of Gage R&R, Cpk, and correlation studies.

STRONGLY PREFERRED

- AEC-Q104, multi-chip module, or system-in-package qualification experience. Multi-die packages, known-good-die strategy, and the assembly yield math that follows.
- Test of co-packaged or chiplet-based devices, including die-to-die interface test and interposer-level bring-up.
- High-speed interface test: LPDDR-class memory, PCIe, automotive Ethernet.
- Automotive functional safety context - ISO 26262, ASIL-B/D concepts, and how safety mechanisms, diagnostic coverage, and latent fault metrics show up as test requirements.
- Radar, high-speed data converter, or RF/millimeter-wave product test background.
- Burn-in and HTOL program bring-up, including working with turnkey burn-in providers.
- Experience standing up test capability at a startup - where the probe card, the socket, the test house relationship, and the test plan are all things you create rather than inherit.

WHY THIS ROLE

Here you will define the test and qualification approach for a co-packaged automotive module built across multiple process technologies, with a high-speed die-to-die interface and a terahertz sensor front-end behind it. Several of the challenges on this program - production test at high frequencies, module qualification against AEC-Q104, known-good-die screening for an advanced interposer - do not have off-the-shelf answers. You will find those answers, and your efforts will help shape the success of our silicon rather than just measure it.

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