Verification Engineer Jobs in San Jose, CA
Verification Engineer jobs in San Jose are concentrated in North San Jose, the Alviso corridor, and Downtown San Jose, with deep demand across semiconductor design, EDA tools, and systems validation. Chip makers, fabless startups, and defense electronics suppliers are among the employers hiring right now, including Broadcom, Astera Labs, and Micron Technology. See the openings below and apply to the ones that match your experience.
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Showing 5 of 61+ Verification Engineer jobs
Responsibilities
- Verify the HBM-based Memory Controller subsystem using SystemVerilog/UVM.
- Develop verification plans, UVM testbenches, test cases, assertions (SVA), and functional coverage.
- Verify the HBM protocol, memory transactions, scheduling, ECC, QoS, power management, and performance.
- Execute regressions, debug RTL/design issues, and drive functional and code coverage closure.
- Collaborate with Architecture, RTL, and Validation teams through verification signoff.
- Strong SystemVerilog/UVM expertise.
- Experience verifying DDR/HBM memory controllers or memory subsystems.
- Good understanding of HBM/DDR protocols, AXI interfaces, and memory architecture.
- Experience with assertions, constrained-random verification, coverage closure, and VIP integration.
- Proficiency with Xcelium/VCS/Questa and scripting (Python/Perl/Shell).
Responsibilities
- Verify the HBM-based Memory Controller subsystem using SystemVerilog/UVM.
- Develop verification plans, UVM testbenches, test cases, assertions (SVA), and functional coverage.
- Verify the HBM protocol, memory transactions, scheduling, ECC, QoS, power management, and performance.
- Execute regressions, debug RTL/design issues, and drive functional and code coverage closure.
- Collaborate with Architecture, RTL, and Validation teams through verification signoff.
- Strong SystemVerilog/UVM expertise.
- Experience verifying DDR/HBM memory controllers or memory subsystems.
- Good understanding of HBM/DDR protocols, AXI interfaces, and memory architecture.
- Experience with assertions, constrained-random verification, coverage closure, and VIP integration.
- Proficiency with Xcelium/VCS/Questa and scripting (Python/Perl/Shell).
See All 61 Verification Engineer Jobs in San Jose
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Find Verification Engineer JobsVerification Engineer Job Market in San Jose
Who's Hiring
Top Industries Hiring
- Electronics & Hardware34
- Technology & Software11
- Telecommunications3
- Manufacturing2
- Artificial Intelligence2
Verification Engineer Jobs in San Jose: Frequently Asked Questions
How do I get a verification engineer job in San Jose?
Focus on San Jose's dense semiconductor and EDA ecosystem, where most openings come from chip design houses, IP licensing firms, and embedded systems companies clustered in North San Jose and the Alviso technology corridor. Hands-on experience with UVM, SystemVerilog, or formal verification tools stands out in this market. Candidates who can show tape-out experience or prior work on SoC verification projects have a clear edge over applicants with general software testing backgrounds.
Which companies hire verification engineers in San Jose?
Companies currently hiring verification engineers in San Jose include Broadcom, Astera Labs, and Micron Technology, per current listings on Migrate Mate as of July 2026. The local market skews heavily toward fabless semiconductor firms, EDA tool vendors, and defense electronics contractors that operate large silicon design centers in and around the city.
Are there remote verification engineer jobs in San Jose?
Yes, though verification engineering is less remote-friendly than many tech roles because RTL simulation, lab bring-up, and hardware debug often require on-site access to lab equipment. About 3% of verification engineer openings tied to San Jose are remote or hybrid as of July 2026, with hybrid arrangements more common than fully remote. Pre-silicon functional verification and coverage closure tasks are the portions most often approved for off-site work by San Jose employers.
How can I get a verification engineer job in San Jose with little or no experience?
The most realistic entry path in San Jose is an internship or associate verification engineer role at one of the city's mid-size fabless semiconductor companies, which regularly hire graduates from nearby programs and provide structured mentorship on UVM methodology. Junior DV engineer positions, FPGA validation roles, and test automation engineering jobs at embedded systems contractors are strong lateral entry points. Building a GitHub portfolio with self-initiated SystemVerilog testbench projects noticeably strengthens applications for these roles locally.
Which industries hire the most verification engineers in San Jose?
San Jose verification engineer roles concentrate in Electronics & Hardware, Technology & Software, and Telecommunications, based on current listings on Migrate Mate as of July 2026. San Jose's position as the historic center of Silicon Valley means semiconductor design and electronic systems development generate a disproportionately large share of local demand compared to any other metro area in the country.
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