ASIC Engineer Jobs in USA with Visa Sponsorship
ASIC Engineer jobs attract strong H-1B visa sponsorship from semiconductor and chip design companies, where the specialty occupation standard is well-established for RTL design, verification, and physical implementation roles. Most employers file LCAs under electrical engineering classifications, and the annual H-1B cap applies unless you join a cap-exempt institution.
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DFT Engineer for ASIC/Chip level ATPG
Broadcom's ASIC Product Division is seeking candidates for a DFT position at our Fort Collins, Colorado, Development Center. The successful candidate will lead DFT programs from chip-level specification through implementation, verification, and product release to production.
The candidate will participate in all phases of SoC DFT activities for Broadcom APD (ASIC Products Division) designs, including DFT architecture, test insertion, verification, pattern generation, coverage improvement, post-silicon debug, and yield improvement to meet product test metrics. Responsibilities also include collaborating with physical design and STA teams for DFT-mode timing closure and directly interfacing with external customers.
Responsibilities:
- Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC.
- Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration.
- Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns.
- Collaborate closely with STA and design integration engineers for timing and design closure.
- Generate, verify, and debug test vectors prior to tapeout release.
- Validate and debug test vectors on ATE during silicon bring-up.
- Assist with silicon failure analysis, diagnostics, and yield improvement efforts.
- Interface with customers, physical design teams, and global test engineering/manufacturing teams.
- Work closely with IP DFT engineers and cross-functional stakeholders.
- Debug customer-returned parts (RMA) on ATE.
- Proficiency in scripting and automation (such as Python, TCL, or C++), with an emphasis on applying AI-augmented development to streamline test flows.
- Develop innovative DFT solutions for advanced process nodes (3nm and beyond).
- Automate DFT and test vector generation flows.
Skills/Experience:
- Strong DFT architecture and implementation background (Scan, BIST, IO/Analog DFT, IJTAG/IEEE 1687, IEEE 1149.1/1149.6)
- Proficiency with EDA tools for scan insertion, compression, and ATPG (e.g., DFT Compiler, TestKompress, TetraMax, FastScan)
- Hands-on experience with memory and logic BIST strategies, verification, and debug across embedded memories (SRAM, CAM, RF, ROM)
- Experience with In-Field testing solutions a plus
- Extensive experience in Verilog coding, testbench development, ATPG pattern generation, simulation, and timing constraints/Test-STA
- Solid foundation in digital/analog circuit design, device physics, silicon manufacturing, synthesis, and transistor reliability
- Strong problem-solving, root-cause debug, statistical process control, and data analysis skills for silicon yield and quality improvement
- Effective cross-functional communication and project management skills to collaborate across physical design, test engineering, and operations
- Experience with ATE silicon bring-up, debug, and high-speed IP/interface testing (SerDes, DDR, PCIe, Ethernet, CXL, Tessent SSN) is a plus
Education & Experience:
Bachelors in Electrical/Electronic/Computer Engineering and 8+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 6+ years of relevant industry experience
Compensation and Benefits
The annual base salary range for this position is USD 109,700.00 To USD 175,500.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Job Description:
DFT Engineer for ASIC/Chip level ATPG
Broadcom's ASIC Product Division is seeking candidates for a DFT position at our Fort Collins, Colorado, Development Center. The successful candidate will lead DFT programs from chip-level specification through implementation, verification, and product release to production.
The candidate will participate in all phases of SoC DFT activities for Broadcom APD (ASIC Products Division) designs, including DFT architecture, test insertion, verification, pattern generation, coverage improvement, post-silicon debug, and yield improvement to meet product test metrics. Responsibilities also include collaborating with physical design and STA teams for DFT-mode timing closure and directly interfacing with external customers.
Responsibilities:
- Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC.
- Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration.
- Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns.
- Collaborate closely with STA and design integration engineers for timing and design closure.
- Generate, verify, and debug test vectors prior to tapeout release.
- Validate and debug test vectors on ATE during silicon bring-up.
- Assist with silicon failure analysis, diagnostics, and yield improvement efforts.
- Interface with customers, physical design teams, and global test engineering/manufacturing teams.
- Work closely with IP DFT engineers and cross-functional stakeholders.
- Debug customer-returned parts (RMA) on ATE.
- Proficiency in scripting and automation (such as Python, TCL, or C++), with an emphasis on applying AI-augmented development to streamline test flows.
- Develop innovative DFT solutions for advanced process nodes (3nm and beyond).
- Automate DFT and test vector generation flows.
Skills/Experience:
- Strong DFT architecture and implementation background (Scan, BIST, IO/Analog DFT, IJTAG/IEEE 1687, IEEE 1149.1/1149.6)
- Proficiency with EDA tools for scan insertion, compression, and ATPG (e.g., DFT Compiler, TestKompress, TetraMax, FastScan)
- Hands-on experience with memory and logic BIST strategies, verification, and debug across embedded memories (SRAM, CAM, RF, ROM)
- Experience with In-Field testing solutions a plus
- Extensive experience in Verilog coding, testbench development, ATPG pattern generation, simulation, and timing constraints/Test-STA
- Solid foundation in digital/analog circuit design, device physics, silicon manufacturing, synthesis, and transistor reliability
- Strong problem-solving, root-cause debug, statistical process control, and data analysis skills for silicon yield and quality improvement
- Effective cross-functional communication and project management skills to collaborate across physical design, test engineering, and operations
- Experience with ATE silicon bring-up, debug, and high-speed IP/interface testing (SerDes, DDR, PCIe, Ethernet, CXL, Tessent SSN) is a plus
Education & Experience:
Bachelors in Electrical/Electronic/Computer Engineering and 8+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 6+ years of relevant industry experience
Compensation and Benefits
The annual base salary range for this position is USD 109,700.00 To USD 175,500.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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Get Access To All JobsTips for Finding Visa Sponsorship as an ASIC Engineer
Align your degree to RTL specializations
H-1B specialty occupation requires a directly related degree. Electrical engineering, computer engineering, or computer science degrees map cleanly to ASIC roles. A general CS degree supporting a physical design position can draw an RFE, so document the coursework overlap in your resume before applying.
Target fabless and IDM hiring cycles
Fabless semiconductor companies and integrated device manufacturers run structured intern-to-full-time pipelines that assume H-1B sponsorship from day one. Migrate Mate lists U.S. employers with verified LCA filing history in chip design, so you can prioritize outreach to teams that have sponsored ASIC engineers before.
Check prevailing wage tiers before accepting offers
ASIC Engineer LCAs are filed at DOL wage levels I through IV. Your offered salary must meet the certified prevailing wage for your work location. Run the OFLC Wage Search using the electrical engineers occupation category before you negotiate, so you know the floor the employer must meet.
Prepare a hardware portfolio for visa documentation
USCIS adjudicators reviewing ASIC petitions respond well to concrete technical evidence. Compile block diagrams, tapeout summaries, or published datasheets that show your RTL or physical design scope. This supporting evidence strengthens specialty occupation arguments if your petition receives a Request for Evidence.
Ask about cap-exempt employer options early
Universities and DOE national laboratories working on custom silicon projects are cap-exempt H-1B employers. If you're open to research-oriented ASIC work, these roles let you skip the annual lottery entirely. Confirm cap-exempt status directly with the employer's HR team before the offer stage.
Verify O*NET classification matches your actual duties
O*NET lists ASIC-relevant tasks under electrical and electronics engineers. Confirm your offer letter and job description reflect those duties, specifically logic design, circuit simulation, or timing closure. Mismatches between the posted title and O*NET task descriptions are a common trigger for specialty occupation RFEs.
Frequently Asked Questions
Does an ASIC Engineer role qualify as a specialty occupation for H-1B purposes?
Yes, in almost all cases. ASIC engineering requires at least a bachelor's degree in electrical engineering, computer engineering, or a closely related field, which satisfies the H-1B specialty occupation definition. Roles focused on RTL design, functional verification, timing analysis, or physical implementation all map clearly to that standard. Where petitions run into trouble is when the job description is written too broadly, so a precise, technically detailed offer letter matters.
Which visa types are realistic for international ASIC Engineers seeking U.S. jobs?
H-1B is the primary path and the most commonly used by semiconductor employers. If you hold an Australian passport, the E-3 visa is an attractive alternative: it has no lottery, an annual cap that has never been exhausted, and renewals every two years. Chilean and Singaporean nationals can explore the H-1B1 visa, which also skips the H-1B lottery and has its own separate cap.
How do I find ASIC Engineer jobs where the employer is already sponsoring visas?
Migrate Mate shows employers with verified LCA filing history for engineering roles, so you can focus your applications on companies that have already sponsored positions like yours rather than companies that are open to it in theory.
Does the type of ASIC work affect sponsorship approval, such as front-end versus back-end roles?
Both front-end (RTL design, functional verification, synthesis) and back-end (floorplanning, place-and-route, timing closure) roles have been successfully sponsored under H-1B. The key is that the position description maps to a degree requirement in a specific engineering discipline. Back-end physical design roles occasionally receive more scrutiny because some employers phrase them in ways that resemble general CAD work, so the job description needs to reference the underlying electrical or computer engineering expertise required.
Can I transfer my H-1B to a new semiconductor employer without losing status?
Yes. H-1B portability lets you start working for a new employer once the new I-129 petition is filed with USCIS, without waiting for approval. You don't need to wait for the new petition to be approved before starting. The new employer must file a full LCA for your new position and location, and your offered compensation must meet the prevailing wage for that worksite.
What is the prevailing wage requirement for sponsored ASIC Engineer jobs?
U.S. employers sponsoring a visa must pay at least the prevailing wage, which is what workers in the same role, area, and experience level typically earn. The Department of Labor sets this rate to make sure companies aren't hiring foreign workers simply because they'd accept lower pay than a U.S. worker. It varies by job title, location, and experience. You can look up current prevailing wage rates for any occupation and location using the OFLC Wage Search page.