Data Center Engineer Jobs in California
Data Center Engineer jobs in California are among the most active in the country, concentrated in the Bay Area, Los Angeles, and Silicon Valley across hyperscale cloud providers, enterprise tech firms, and colocation operators serving every level from entry-level operations technician through senior infrastructure engineer. Major employers with lasting California footprints include Google, Meta, and Equinix, all of whom operate large-scale data center facilities requiring ongoing engineering talent. The most in-demand specialties are power and cooling systems, network infrastructure, and automation and DCIM platforms. Find a role that fits below and apply directly.
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Showing 1 of 86+ Data Center Engineer jobs
Please Note:
To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.
Advancing the World's Technology Together
Our technology solutions power the tools you use every day-including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future.
We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.
Principal Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU
What You'll Do
Architecture Research Lab is focused on researching next-generation CPU (RISC-V) microarchitecture and performance for emerging computing workloads. We explore new architectural ideas, evaluate their performance potential, and rapidly turn promising concepts into working designs that can be validated on real silicon. Our research is driven by emerging opportunities in data center and agentic AI workloads, where we investigate how CPU architecture can evolve to meet new performance and efficiency requirements. We also explore CPU-memory co-design from the CPU perspective, in alignment with the broader shift toward memory-centric architectures. A distinctive aspect of our team is the way we approach architecture research. We develop and apply AI-driven methodologies to accelerate architectural exploration, broaden the design space we can investigate, and quickly iterate from ideas to implementation and silicon validation. Rather than simply following established design flows, we continuously seek new ways to explore, evaluate, and realize CPU architectures. The role offers an opportunity to work across the full spectrum of architecture research—from workload and performance analysis, microarchitectural innovation, and architectural modeling to implementation and silicon validation—while helping shape new methodologies for how future CPUs are designed.
Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy
Job ID: 43044
As a CPU Architecture & Performance Engineer, you will define the architectural vision and performance direction for next-generation CPU platforms. You will identify opportunities across emerging workloads, shape long-term architectural strategies, develop and refine performance models, and drive new microarchitectural concepts across multiple architectural domains. You will work closely with RTL design teams and cross-functional engineering partners to translate architectural vision into implementable designs, influence key technical decisions, and validate architectural choices from modeling through silicon. The role carries broad technical ownership, with the opportunity to establish new research directions, drive architecture across multiple generations of CPUs, and shape the fundamental design choices that determine future CPU performance and capabilities.
- Define the application-specialization direction for next-generation CPU cores, including agentic AI and memory-centric architectures, and lead the overall microarchitectural vision
- Lead end-to-end performance analysis using architectural simulators and RTL, guiding key architectural trade-offs and decisions
- Translate workload characterization and performance insights into architectural requirements and long-term design direction
- Drive architecture-to-implementation alignment with design teams, ensuring architectural intent is carried through RTL and silicon
- Mentor Senior and Staff engineers and provide technical leadership across multiple projects and architectural domains
- Drive research and technical contributions leading to patents and publications
What You Bring
- Master's degree in Computer Engineering, Computer Science, or a related field with 18+ years of relevant experience, or PhD with 15+ years of relevant experience
- 5+ years of experience in CPU microarchitecture, architecture research, or performance engineering, with a demonstrated track record of driving architectural direction
- Extensive experience designing and evaluating high-performance CPU architectures, including RISC-V, ARM, or x86 cores; experience with GPU/NPU vector or accelerator architectures is also relevant
- Proven ability to use quantitative performance analysis and modeling to identify architectural opportunities, evaluate system-level trade-offs, and influence major microarchitectural decisions
- Deep expertise in at least one major microarchitectural domain, with the ability to drive architectural direction and technical decisions in that area:
- Front-end: Branch prediction, fetch/decode, instruction delivery, and decoupled front-end architectures
- Mid-end: Out-of-order execution, scheduling, RVV/SIMD, vector execution, or matrix/tensor acceleration
- Back-end: Load/store units, MSHRs, cache and memory systems, prefetching, or irregular memory access optimization
- Hands-on experience building, extending, and applying architectural simulators and performance models, such as gem5, to guide architecture decisions
- Strong programming skills in C/C++ and Python, with experience developing tools and automation for performance analysis and architectural exploration
- Demonstrated ability to take architectural concepts from research and modeling through RTL implementation and silicon validation
Preferred Qualifications
- Experience defining or influencing CPU architecture for emerging workloads, particularly AI/ML, agentic AI, or data center applications
- Experience with AI-driven architecture and design methodologies, including AI-assisted architecture exploration, high-level design, or RTL generation
- Strong perspective on memory-centric architectures and CPU-memory co-design, with experience translating memory-system characteristics into CPU architectural opportunities
- Experience driving system-level PPA trade-offs across performance, power, area, and implementation complexity
- Experience taking architectural concepts through RTL implementation, tape-out, and silicon validation
- Experience leading cross-functional architecture initiatives and influencing technical direction across multiple engineering teams
- Proven ability to mentor and develop senior technical engineers and shape architecture research across multiple domains
- Track record of impactful architectural innovation through patents, publications, or deployed products
- You're inclusive, adapting your style to the situation and diverse global norms of our people.
- You approach challenges with curiosity and resilience, seeking data to help build understanding.
- You're collaborative, building relationships, humbly offering support and openly welcoming approaches.
- Innovative and creative, you proactively explore new ideas and adapt quickly to change
#LI-SF1
Equal Opportunity Employment Policy
Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.
When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.
Our Commitment to Innovation and Fairness
At Samsung Semiconductor, we use Artificial Intelligence (AI) tools in the recruitment process to enhance efficiency. However, AI is used as a support tool, not a final decision-maker. All hiring decisions are made by our human recruiting team and hiring managers to ensure every candidate is evaluated fairly and holistically.
Recruiting Agency Policy
We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings.
Applicant AI Use Policy
At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we ask that candidates rely on their own knowledge and skills throughout the process. AI tools may be used for basic preparation, grammar, and research, but should not be used to generate or assist with submitted content or live interview responses. If we determine that AI is being used outside these guidelines, we reserve the right to pause or end the interview, and your candidacy may be disqualified.
Trade Secret Notice
By submitting an application, you agree not to disclose to Samsung—or encourage Samsung to use—any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.
Applicant Privacy Policy
https://semiconductor.samsung.com/about-us/careers/us/privacy/
Please Note:
To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.
Advancing the World's Technology Together
Our technology solutions power the tools you use every day-including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future.
We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.
Principal Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU
What You'll Do
Architecture Research Lab is focused on researching next-generation CPU (RISC-V) microarchitecture and performance for emerging computing workloads. We explore new architectural ideas, evaluate their performance potential, and rapidly turn promising concepts into working designs that can be validated on real silicon. Our research is driven by emerging opportunities in data center and agentic AI workloads, where we investigate how CPU architecture can evolve to meet new performance and efficiency requirements. We also explore CPU-memory co-design from the CPU perspective, in alignment with the broader shift toward memory-centric architectures. A distinctive aspect of our team is the way we approach architecture research. We develop and apply AI-driven methodologies to accelerate architectural exploration, broaden the design space we can investigate, and quickly iterate from ideas to implementation and silicon validation. Rather than simply following established design flows, we continuously seek new ways to explore, evaluate, and realize CPU architectures. The role offers an opportunity to work across the full spectrum of architecture research—from workload and performance analysis, microarchitectural innovation, and architectural modeling to implementation and silicon validation—while helping shape new methodologies for how future CPUs are designed.
Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy
Job ID: 43044
As a CPU Architecture & Performance Engineer, you will define the architectural vision and performance direction for next-generation CPU platforms. You will identify opportunities across emerging workloads, shape long-term architectural strategies, develop and refine performance models, and drive new microarchitectural concepts across multiple architectural domains. You will work closely with RTL design teams and cross-functional engineering partners to translate architectural vision into implementable designs, influence key technical decisions, and validate architectural choices from modeling through silicon. The role carries broad technical ownership, with the opportunity to establish new research directions, drive architecture across multiple generations of CPUs, and shape the fundamental design choices that determine future CPU performance and capabilities.
- Define the application-specialization direction for next-generation CPU cores, including agentic AI and memory-centric architectures, and lead the overall microarchitectural vision
- Lead end-to-end performance analysis using architectural simulators and RTL, guiding key architectural trade-offs and decisions
- Translate workload characterization and performance insights into architectural requirements and long-term design direction
- Drive architecture-to-implementation alignment with design teams, ensuring architectural intent is carried through RTL and silicon
- Mentor Senior and Staff engineers and provide technical leadership across multiple projects and architectural domains
- Drive research and technical contributions leading to patents and publications
What You Bring
- Master's degree in Computer Engineering, Computer Science, or a related field with 18+ years of relevant experience, or PhD with 15+ years of relevant experience
- 5+ years of experience in CPU microarchitecture, architecture research, or performance engineering, with a demonstrated track record of driving architectural direction
- Extensive experience designing and evaluating high-performance CPU architectures, including RISC-V, ARM, or x86 cores; experience with GPU/NPU vector or accelerator architectures is also relevant
- Proven ability to use quantitative performance analysis and modeling to identify architectural opportunities, evaluate system-level trade-offs, and influence major microarchitectural decisions
- Deep expertise in at least one major microarchitectural domain, with the ability to drive architectural direction and technical decisions in that area:
- Front-end: Branch prediction, fetch/decode, instruction delivery, and decoupled front-end architectures
- Mid-end: Out-of-order execution, scheduling, RVV/SIMD, vector execution, or matrix/tensor acceleration
- Back-end: Load/store units, MSHRs, cache and memory systems, prefetching, or irregular memory access optimization
- Hands-on experience building, extending, and applying architectural simulators and performance models, such as gem5, to guide architecture decisions
- Strong programming skills in C/C++ and Python, with experience developing tools and automation for performance analysis and architectural exploration
- Demonstrated ability to take architectural concepts from research and modeling through RTL implementation and silicon validation
Preferred Qualifications
- Experience defining or influencing CPU architecture for emerging workloads, particularly AI/ML, agentic AI, or data center applications
- Experience with AI-driven architecture and design methodologies, including AI-assisted architecture exploration, high-level design, or RTL generation
- Strong perspective on memory-centric architectures and CPU-memory co-design, with experience translating memory-system characteristics into CPU architectural opportunities
- Experience driving system-level PPA trade-offs across performance, power, area, and implementation complexity
- Experience taking architectural concepts through RTL implementation, tape-out, and silicon validation
- Experience leading cross-functional architecture initiatives and influencing technical direction across multiple engineering teams
- Proven ability to mentor and develop senior technical engineers and shape architecture research across multiple domains
- Track record of impactful architectural innovation through patents, publications, or deployed products
- You're inclusive, adapting your style to the situation and diverse global norms of our people.
- You approach challenges with curiosity and resilience, seeking data to help build understanding.
- You're collaborative, building relationships, humbly offering support and openly welcoming approaches.
- Innovative and creative, you proactively explore new ideas and adapt quickly to change
#LI-SF1
Equal Opportunity Employment Policy
Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.
When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.
Our Commitment to Innovation and Fairness
At Samsung Semiconductor, we use Artificial Intelligence (AI) tools in the recruitment process to enhance efficiency. However, AI is used as a support tool, not a final decision-maker. All hiring decisions are made by our human recruiting team and hiring managers to ensure every candidate is evaluated fairly and holistically.
Recruiting Agency Policy
We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings.
Applicant AI Use Policy
At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we ask that candidates rely on their own knowledge and skills throughout the process. AI tools may be used for basic preparation, grammar, and research, but should not be used to generate or assist with submitted content or live interview responses. If we determine that AI is being used outside these guidelines, we reserve the right to pause or end the interview, and your candidacy may be disqualified.
Trade Secret Notice
By submitting an application, you agree not to disclose to Samsung—or encourage Samsung to use—any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.
Applicant Privacy Policy
https://semiconductor.samsung.com/about-us/careers/us/privacy/
See All 86 Data Center Engineer Jobs in California
Find roles in California that match your experience and apply in just a few clicks.
Find Data Center Engineer JobsData Center Engineer Jobs by City in California
Where California roles are concentrated, by current openings.
Data Center Engineer Job Market in California
A snapshot from current California openings, updated as new roles post.
Who's Hiring
Top Industries Hiring
- Electronics & Hardware
- Technology & Software
- Science & Research
- Retail
- Law & Legal Services
What California Employers Look For
The qualifications that appear most often in data center engineer jobs across California.
- Associate or bachelor's degree in electrical engineering, computer science, or related field
- Experience with data center power systems including UPS, PDUs, and generator operations
- Hands-on knowledge of cooling infrastructure such as CRAC units and hot-aisle containment
- Familiarity with network hardware installation, cable management, and structured cabling standards
- CompTIA Data+, DCDC, or equivalent data center infrastructure certification preferred
- Experience with DCIM software platforms and change management ticketing systems
Data Center Engineer Jobs in California: Frequently Asked Questions
How do you become a data center engineer in California?
Most California employers require at least an associate degree in electrical engineering, information technology, or a related field, though a bachelor's degree is increasingly standard for senior roles. California does not mandate a state-issued license specific to data center engineering, but electricians working on electrical systems within facilities must hold a California Electrical Certification through the Department of Industrial Relations. Industry credentials such as the Uptime Institute's AFCOM CDCP or CompTIA Server+ strengthen candidacy considerably across the California market.
Which companies hire data center engineers in California?
Employers hiring data center engineers in California right now include Tesla, Meta, and GEICO, based on current listings on Migrate Mate as of October 2026. California's density of hyperscale cloud campuses, colocation providers, and enterprise tech headquarters means openings exist across a wide range of employer types and facility scales.
Which California cities have the most data center engineer jobs?
San Jose, San Francisco, and Santa Clara have the most data center engineer openings in California. The Bay Area and Silicon Valley drive the largest concentration due to the headquarters and campus operations of major cloud and tech firms, while Los Angeles and San Diego have grown as secondary hubs anchored by enterprise colocation facilities and media-tech companies requiring dedicated infrastructure teams.
Are there remote data center engineer jobs in California?
Yes, but they're rare. Data center engineering is fundamentally a hands-on role requiring physical presence for hardware installation, maintenance, and incident response, so fully remote positions are the exception. About 59% of data center engineer openings tied to California are remote or hybrid as of October 2026, and those tend to concentrate in planning, DCIM monitoring, or capacity management functions that do not require constant floor access.
How can I get hired as a data center engineer in California with little or no experience?
The most realistic entry path is a data center technician or operations technician role, which focuses on hands-on hardware tasks and requires less design experience. Large California colocation operators like Equinix and CyrusOne run structured associate technician programs that accept candidates from IT support, field service technician, or network operations backgrounds. Earning a CompTIA Server+ or an Uptime Institute CDCP credential before applying signals readiness and separates entry-level candidates on California employer screening lists.
Where can I find and apply to data center engineer jobs in California?
You can find and apply to data center engineer jobs in California on Migrate Mate, which lists current California openings across facility types, employer sizes, and specialties. Find a role that fits and apply directly from the listing.
See All 86 Data Center Engineer Jobs in California
Find roles in California that match your experience and apply in just a few clicks.
Find Data Center Engineer Jobs