Engineering Senior Manager Jobs in Cupertino, CA
Engineering Senior Manager jobs in Cupertino concentrate in the North Vallco and Main Street corridors, along with the tech campuses lining De Anza Boulevard, across consumer electronics, semiconductor design, and enterprise software. Employers actively hiring include Apple, Amazon, and Amazon Web Services. Scan the live roles below and apply to whichever ones fit.
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Showing 5 of 590+ Engineering Senior Manager jobs
DESCRIPTION
We’re looking for a Senior Manager, Physical Design Engineering to build and lead a world-class Physical Design team delivering multi-billion-transistor ML accelerator SoCs on latest tech nodes.
Key job responsibilities
- Build, hire, and develop a physical design team of 10-15 engineers. Own headcount planning, performance management, career growth, and organizational scaling to support multiple concurrent tapeouts.
- Own the physical design strategy and execution roadmap across Inferentia, Trainium, and future products: implementation architecture, hierarchical methodology, PPA target-setting, and technology node adoption.
- Institutionalize continuous PPA improvement: benchmarking frameworks, regression tracking, design-quality dashboards, post-tapeout retrospectives, and structured improvement programs that compound across generations.
- Provide hands-on technical leadership on the hardest problems: multi-GHz timing closure, PDN architecture, high-speed I/O physical design, and 2.5D / 3D cross-die integration.
- Lead technology node enablement for 2nm and beyond: PDK evaluation, reference flow development, PPA pathfinding, and adoption recommendations.
- Define and deploy innovative RTL2GDS methodologies and CAD flows. Champion AI/ML-augmented design automation (RL-placement, ML-guided ECO, predictive analytics). Optimize cloud infrastructure for PD compute.
- Serve as part of senior technical interface with foundry partners and EDA vendors on tool roadmap, co-development, and technology co-optimization.
- Own tapeout execution: readiness reviews, foundry submittal, mask data coordination, and post-silicon yield learning. Drive cross-functional alignment with RTL, DFT, STA, Package, and Validation teams.
BASIC QUALIFICATIONS
- 5+ years people management leading PD teams of 8+ engineers, including hiring, performance management, and organizational growth.
- 10+ years hands-on ASIC/SoC physical design across multiple advanced nodes (7nm, 5nm, 3nm) with multiple successful tapeouts.
- Technical depth across full RTL-to-GDSII: floorplanning, CTS, routing, timing closure, PDN design, IR-drop/EM signoff, physical verification, and tapeout.
- Mastery of both EDA ecosystems: Synopsys (Fusion Compiler/ICC2, PrimeTime, StarRC, RedHawk-SC) AND Cadence (Innovus, Tempus, Quantus, Voltus). Physical verification with Siemens Calibre (DRC, LVS, PERC).
- Deep expertise in advanced STA (MMMC, POCV/AOCV, SSTA, PBA, IR-aware timing) and power integrity (static/dynamic IR-drop, EM, rush current, Ldi/dt, package-aware analysis).
- Proven expertise in high-speed PD (multi-GHz datapaths, SerDes, DDR5, HBM, PCIe Gen5+, UCIe) and low-power design (UPF, power gating, DVFS, retention).
- Experience with hierarchical methodologies for very large SoCs (>1B transistors). Expert scripting in TCL, Python, Perl.
PREFERRED QUALIFICATIONS
- Experience leading PD for AI/ML accelerators, GPUs, or high-performance data-center SoCs at leading semiconductor companies or hyperscalers.
- Direct 3nm GAA/Nanosheet experience; 2nm or sub-2nm engagement. Familiarity with CFET and backside power delivery (BSPDN).
- Quantifiable track record of continuous PPA improvement and metric-driven flow development across multiple projects and nodes.
- Strong program execution: managing concurrent tapeouts, milestone tracking, risk identification, and executive communication.
- Hands-on 2.5D/3D integration experience (CoWoS, EMIB, InFO, SoIC, Foveros) and chiplet strategy with UCIe.
- Track record deploying AI/ML-driven design methodologies in production flows.
- Experience with CPO, HBM4, silicon photonics, or CXL physical design.
- Multi-foundry technology assessment experience (TSMC, Samsung, Intel Foundry Services).
- Experience managing geographically distributed teams (U.S., Israel, global).
- Experience scaling PD organizations through 2x–3x growth. Patent portfolio or industry standards contributions (UCIe, IEEE).
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.
Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.
The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.
USA, CA, Cupertino - 239,600.00 - 324,100.00 USD annually
USA, TX, Austin - 208,300.00 - 281,800.00 USD annually
DESCRIPTION
We’re looking for a Senior Manager, Physical Design Engineering to build and lead a world-class Physical Design team delivering multi-billion-transistor ML accelerator SoCs on latest tech nodes.
Key job responsibilities
- Build, hire, and develop a physical design team of 10-15 engineers. Own headcount planning, performance management, career growth, and organizational scaling to support multiple concurrent tapeouts.
- Own the physical design strategy and execution roadmap across Inferentia, Trainium, and future products: implementation architecture, hierarchical methodology, PPA target-setting, and technology node adoption.
- Institutionalize continuous PPA improvement: benchmarking frameworks, regression tracking, design-quality dashboards, post-tapeout retrospectives, and structured improvement programs that compound across generations.
- Provide hands-on technical leadership on the hardest problems: multi-GHz timing closure, PDN architecture, high-speed I/O physical design, and 2.5D / 3D cross-die integration.
- Lead technology node enablement for 2nm and beyond: PDK evaluation, reference flow development, PPA pathfinding, and adoption recommendations.
- Define and deploy innovative RTL2GDS methodologies and CAD flows. Champion AI/ML-augmented design automation (RL-placement, ML-guided ECO, predictive analytics). Optimize cloud infrastructure for PD compute.
- Serve as part of senior technical interface with foundry partners and EDA vendors on tool roadmap, co-development, and technology co-optimization.
- Own tapeout execution: readiness reviews, foundry submittal, mask data coordination, and post-silicon yield learning. Drive cross-functional alignment with RTL, DFT, STA, Package, and Validation teams.
BASIC QUALIFICATIONS
- 5+ years people management leading PD teams of 8+ engineers, including hiring, performance management, and organizational growth.
- 10+ years hands-on ASIC/SoC physical design across multiple advanced nodes (7nm, 5nm, 3nm) with multiple successful tapeouts.
- Technical depth across full RTL-to-GDSII: floorplanning, CTS, routing, timing closure, PDN design, IR-drop/EM signoff, physical verification, and tapeout.
- Mastery of both EDA ecosystems: Synopsys (Fusion Compiler/ICC2, PrimeTime, StarRC, RedHawk-SC) AND Cadence (Innovus, Tempus, Quantus, Voltus). Physical verification with Siemens Calibre (DRC, LVS, PERC).
- Deep expertise in advanced STA (MMMC, POCV/AOCV, SSTA, PBA, IR-aware timing) and power integrity (static/dynamic IR-drop, EM, rush current, Ldi/dt, package-aware analysis).
- Proven expertise in high-speed PD (multi-GHz datapaths, SerDes, DDR5, HBM, PCIe Gen5+, UCIe) and low-power design (UPF, power gating, DVFS, retention).
- Experience with hierarchical methodologies for very large SoCs (>1B transistors). Expert scripting in TCL, Python, Perl.
PREFERRED QUALIFICATIONS
- Experience leading PD for AI/ML accelerators, GPUs, or high-performance data-center SoCs at leading semiconductor companies or hyperscalers.
- Direct 3nm GAA/Nanosheet experience; 2nm or sub-2nm engagement. Familiarity with CFET and backside power delivery (BSPDN).
- Quantifiable track record of continuous PPA improvement and metric-driven flow development across multiple projects and nodes.
- Strong program execution: managing concurrent tapeouts, milestone tracking, risk identification, and executive communication.
- Hands-on 2.5D/3D integration experience (CoWoS, EMIB, InFO, SoIC, Foveros) and chiplet strategy with UCIe.
- Track record deploying AI/ML-driven design methodologies in production flows.
- Experience with CPO, HBM4, silicon photonics, or CXL physical design.
- Multi-foundry technology assessment experience (TSMC, Samsung, Intel Foundry Services).
- Experience managing geographically distributed teams (U.S., Israel, global).
- Experience scaling PD organizations through 2x–3x growth. Patent portfolio or industry standards contributions (UCIe, IEEE).
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.
Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.
The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.
USA, CA, Cupertino - 239,600.00 - 324,100.00 USD annually
USA, TX, Austin - 208,300.00 - 281,800.00 USD annually
See All 590+ Engineering Senior Manager Jobs in Cupertino
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Find JobsEngineering Senior Manager Job Market in Cupertino
Who's Hiring
- Apple425
- Amazon71
- Amazon Web Services71
- Hewlett Packard Enterprise | HPE24
Top Industries Hiring
- Electronics & Hardware
- Distribution & Wholesale
Engineering Senior Manager Jobs in Cupertino: Frequently Asked Questions
How do I get a engineering senior manager job in Cupertino?
The strongest path into an engineering senior manager role in Cupertino is through the city's dense concentration of consumer electronics and semiconductor companies, where cross-functional leadership experience carries real weight. Candidates who have managed multi-disciplinary hardware-software teams stand out, as do those with a history of shipping products at scale. Targeting mid-size chip design firms and the larger campus employers along De Anza Boulevard gives you the broadest set of open requisitions in one area.
Which companies hire engineering senior managers in Cupertino?
Employers hiring engineering senior managers in Cupertino right now include Apple, Amazon, and Amazon Web Services, based on current listings on Migrate Mate as of September 2026. Cupertino's employer base skews heavily toward large consumer tech and semiconductor companies with dedicated hardware, systems, and platform engineering organizations that regularly staff senior manager roles.
Are there remote engineering senior manager jobs in Cupertino?
Yes, though engineering senior manager roles tied to hardware or lab-dependent teams are predominantly on-site. About 0% of engineering senior manager openings tied to Cupertino are remote or hybrid as of September 2026, with flexibility concentrated in program management, systems engineering, and software platform teams rather than in roles that require hands-on lab or manufacturing oversight.
How can I get a engineering senior manager job in Cupertino with little or no experience?
The most realistic entry path in Cupertino is moving into a senior manager seat from a staff or principal engineer role within one of the city's large consumer tech campuses, where internal promotion pipelines are well-established. Smaller semiconductor design firms and hardware startups clustered near Cupertino also hire engineering leads with less formal management tenure, valuing hands-on technical depth over years in a titled role. Building visibility through technical presentations and open-source contributions relevant to silicon or embedded systems sharpens your profile for local hiring managers.
Which industries hire the most engineering senior managers in Cupertino?
The sectors hiring the most engineering senior managers in Cupertino are Electronics & Hardware and Distribution & Wholesale, based on current listings on Migrate Mate as of September 2026. Cupertino's identity as a global consumer electronics hub means these sectors maintain unusually large and sustained engineering management headcounts compared to similarly sized cities.
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