H-1B Visa Senior Asic Design Engineer Jobs
Senior ASIC Design Engineers are among the most consistently sponsored roles in the H-1B visa category, with chip design expertise sitting firmly within USCIS specialty occupation criteria. Semiconductor companies filing LCAs under SOC codes for electrical and electronics engineers regularly clear H-1B visa cap-subject filings for this role.
Find H-1B Visa Senior Asic Design Engineer JobsOverview
Showing 5 of 192+ Senior Asic Design Engineer jobs










See all 192+ Senior Asic Design Engineer Jobs
Sign up for free to unlock all listings, filter by visa type, and get alerts for new Senior Asic Design Engineer roles.
Get Access To All Jobs
INTRODUCTION
Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens.
Applications are accepted until further notice.
Meet the Team
The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Your Impact
You will be in the Silicon One development organization as an ASIC Design for Test Engineer with a primary focus on Design-for-Test. You will work with frontend RTL teams, backend Physical Design teams to understand chip architecture and drive DFT requirements early in the design cycle. You will:
- Implement the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics needs of the designs.
- Create and enhance automation scripts to improve implementation robustness and efficiency.
- Work closely with the Design, Design Verification, and Physical Design teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
- Collaborate with team members to validate test timing and logic equivalency of designs using SystemVerilog.
- Utilize ATPG and EDA tools (TestMax, Tetramax, Tessent, PrimeTime) for test pattern generation and analysis.
MINIMUM QUALIFICATIONS
- Meet one of the following (completed within the past 3 years or expected to be completed within the next 12 months):
- A Master's degree with 0 years of work experience; or
- A Bachelor's degree with 2 years of work experience.
- Qualifying education and work experience should be in ASIC Engineering or a related field.
- Foundational understanding or academic/internship exposure to JTAG protocols, scan architectures, and BIST (Built-In Self-Test, including memory BIST and boundary scan).
- Familiarity or introductory hands-on exposure to EDA and ATPG tools along with scripting or coding skills in Python, Tcl, or Perl.
- Experience working with gate-level simulations and debugging using simulators like VCS.
PREFERRED QUALIFICATIONS
- Practical experience or strong coursework in verification skills, including SystemVerilog, logic equivalency checking, and test-timing validation.
- Understanding of basic VLSI circuit physical behaviors in silicon (such as electromigration and temperature/voltage variation effects) and familiarity with basic timing concepts (setup/hold times, metastability).
- Exposure to post-silicon validation using DFT patterns and Test Static Timing Analysis.
- Strong verbal and written communication skills to collaborate effectively with frontend RTL, backend physical design, and verification teams.
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Message to applicants applying to work in the U.S. and/or Canada:
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.
U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:
- 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
- Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
- Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
- 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:
- .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
- 1.5% of incentive target for each 1% of attainment between 50% and 75%;
- 1% of incentive target for each 1% of attainment between 75% and 100%; and
- Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.
The applicable full salary ranges for this position, by specific state, are listed below:
New York City Metro Area:
$125,700.00 - $203,100.00
Non-Metro New York state & Washington state:
$111,700.00 - $180,800.00
- For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.
See all 192+ H-1B Visa Senior Asic Design Engineer Jobs
Sign up for free to unlock all listings, filter by visa type, and get alerts for new H-1B Visa Senior Asic Design Engineer Jobs.
Get Access To All JobsTips for Finding H-1B Visa Sponsorship as a Senior Asic Design Engineer
Align your portfolio with LCA job codes
ASIC roles are filed under specific SOC codes in the LCA. Pull your target employers' recent LCA filings through the OFLC Wage Search to confirm they're using the occupation code that matches your RTL, synthesis, or physical design specialization.
Verify your specialty occupation documentation early
USCIS scrutinizes whether ASIC design roles require a directly related degree. Gather transcripts showing coursework in digital logic, VLSI, or microelectronics, and document any gap between your degree title and the specific design discipline your role covers.
Target fabless and IDM semiconductor employers specifically
Chip design roles requiring H-1B sponsorship are concentrated in fabless semiconductor firms and integrated device manufacturers. Search Migrate Mate to filter employers with active H-1B LCA filing history for ASIC and chip design positions.
Clarify the prevailing wage tier before negotiating
DOL assigns ASIC design roles to wage levels based on experience and supervisory responsibility. The LCA locks in a wage floor your employer must meet, so understand which tier your role maps to using the OFLC Wage Search before your offer conversation.
Request concurrent premium processing during offer stage
USCIS premium processing cuts adjudication to 15 business days. For senior-level ASIC roles with project start dates tied to tapeout schedules, ask your employer explicitly to elect premium processing when filing the I-129 petition.
Document proprietary tool experience for RFE defense
If USCIS issues an RFE questioning specialty occupation, your employer's response is stronger when your offer letter and support letter reference specific EDA tools, design flows, or process nodes. Flag these details to your employer's attorney before the petition is drafted.
H-1B Visa Senior Asic Design Engineer: Frequently Asked Questions
Does a Senior ASIC Design Engineer role qualify as a specialty occupation for H-1B purposes?
Yes. USCIS consistently classifies ASIC design roles as specialty occupations because the work requires at minimum a bachelor's degree in electrical engineering, computer engineering, or a directly related field. Employers strengthen the petition by documenting that the role involves RTL coding, synthesis, timing closure, or physical design work that cannot be performed without that specific degree background.
Which employers sponsor H-1B visas for ASIC design roles?
Fabless semiconductor companies, integrated device manufacturers, and large technology firms with in-house silicon teams are the primary H-1B sponsors for ASIC design positions. You can search Migrate Mate to see employers with verified LCA filing history for chip design roles, which shows real sponsorship activity rather than company self-reported claims.
How does the H-1B cap lottery affect ASIC design job timelines?
Cap-subject H-1B registrations open in March each year, with selections announced shortly after. If selected, the earliest employment start date is October 1. For ASIC roles tied to tapeout milestones, this timeline matters: start your employer conversations by late fall or early winter to give enough lead time for the March registration window and any necessary OPT cap-gap coverage.
What prevailing wage level typically applies to senior-level ASIC positions?
DOL assigns prevailing wage levels based on the complexity of duties, supervision exercised, and experience required. Senior ASIC roles with independent project ownership or team lead responsibilities typically fall at Level III or Level IV under the relevant SOC code. Your employer must certify the LCA at a wage that meets or exceeds the DOL-determined threshold for your specific job location.
Can an ASIC design engineer on OPT bridge to H-1B without a gap in work authorization?
Yes, through the cap-gap rule. If your OPT expires before October 1 and your H-1B petition is filed before your OPT end date, your work authorization automatically extends through September 30 of that year. STEM OPT holders have a longer OPT runway, which reduces cap-gap risk. Confirm your I-20 end date and EAD expiration with your DSO as soon as you receive an H-1B selection notice.