H-1B1 Chile Visa AI ML Engineer Jobs
AI ML Engineer jobs in the U.S. are open to Chilean nationals through H-1B1 Chile visa sponsorship, a consulate-only process with a 1,400-visa annual cap that almost never fills. No lottery, no USCIS petition, and your degree in computer science, data science, or a related technical field directly satisfies the specialty occupation requirement.
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Get Access To All JobsMinimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 10 years of experience with ASIC or SoC design.
- Experience with power design, power modeling, power architecture, or power reduction methodologies/techniques.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 5 years of experience managing mid-sized ASIC/SOC design teams with focus on power design and optimization.
- Experience defining and implementing chip-wide power management architectures and designs.
- Experience in power modeling, measurement, and correlation across the pre- and post-silicon phases.
- Understanding of modern power and thermal management techniques at both the silicon and system levels (including Dynamic Voltage and Frequency Scaling (DVFS), Turboing, Thermal Management, and System-Level Tradeoffs).
- Ability to solve open-ended power and performance problems under ambiguity.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Power Design Manager within Google's silicon team, you will help deliver solutions that have a substantive impact on the technical infrastructure that enables Google. You will provide technical leadership to a group of power design engineers in an innovative and fast-paced environment, with a focus on ASIC power architecture, design and project execution. You will own and drive complex technical projects from the concept/planning stage through execution and closure. You will bring out the best in your team to deliver designs that work for the first time with optimal power. You will bring your knowledge and experience in large SoC power architecture and design, ability to work with IP and chip vendors and manufacturers, and ability to work across organizational boundaries to identify the right people to provide technical input and execution to deliver SoC-centric products that are key to Google's computing infrastructure.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits
Responsibilities
- Manage a power design team responsible for power architecture, power optimization and system power integration.
- Lead an experienced team, define the processes, methods and tools to continuously improve the power efficiency of the TPU designs.
- Contribute to design power modeling and drive convergence to power targets.
- Investigate, specify, and deploy architectural and microarchitectural power optimization techniques. Define best practices and methodologies to achieve low-power RTL designs.
- Collaborate with cross-functional software and system teams to create novel power management architectures to meet power goals.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 10 years of experience with ASIC or SoC design.
- Experience with power design, power modeling, power architecture, or power reduction methodologies/techniques.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 5 years of experience managing mid-sized ASIC/SOC design teams with focus on power design and optimization.
- Experience defining and implementing chip-wide power management architectures and designs.
- Experience in power modeling, measurement, and correlation across the pre- and post-silicon phases.
- Understanding of modern power and thermal management techniques at both the silicon and system levels (including Dynamic Voltage and Frequency Scaling (DVFS), Turboing, Thermal Management, and System-Level Tradeoffs).
- Ability to solve open-ended power and performance problems under ambiguity.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Power Design Manager within Google's silicon team, you will help deliver solutions that have a substantive impact on the technical infrastructure that enables Google. You will provide technical leadership to a group of power design engineers in an innovative and fast-paced environment, with a focus on ASIC power architecture, design and project execution. You will own and drive complex technical projects from the concept/planning stage through execution and closure. You will bring out the best in your team to deliver designs that work for the first time with optimal power. You will bring your knowledge and experience in large SoC power architecture and design, ability to work with IP and chip vendors and manufacturers, and ability to work across organizational boundaries to identify the right people to provide technical input and execution to deliver SoC-centric products that are key to Google's computing infrastructure.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits
Responsibilities
- Manage a power design team responsible for power architecture, power optimization and system power integration.
- Lead an experienced team, define the processes, methods and tools to continuously improve the power efficiency of the TPU designs.
- Contribute to design power modeling and drive convergence to power targets.
- Investigate, specify, and deploy architectural and microarchitectural power optimization techniques. Define best practices and methodologies to achieve low-power RTL designs.
- Collaborate with cross-functional software and system teams to create novel power management architectures to meet power goals.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
See all 380+ H-1B1 Chile Visa AI ML Engineer Jobs
Sign up for free to unlock all listings, filter by visa type, and get alerts for new H-1B1 Chile Visa AI ML Engineer Jobs.
Get Access To All JobsTips for Finding Visa Sponsorship as an AI ML Engineer
Translate your Chilean credentials for U.S. hiring managers
Chilean universities follow a licenciatura or title system that U.S. recruiters often can't map to a four-year bachelor's degree. Get a credential evaluation from a NACES-approved evaluator before applying so your degree clearly satisfies the H-1B1 visa specialty occupation requirement.
Use OFLC Wage Search to anchor your salary negotiation
Your employer's Labor Condition Application must certify they'll pay the prevailing wage for your SOC code. Look up the DOL wage level for AI ML Engineer roles in your target metro before your first offer conversation so you're negotiating from the correct floor, not below it.
Search for H-1B1 Chile employers on Migrate Mate
Migrate Mate filters job listings by H-1B1 Chile visa sponsorship history, so you can target AI ML Engineer roles at companies that have already filed LCAs for Chilean nationals rather than spending time on employers unfamiliar with the process.
Confirm the role's SOC code maps to a specialty occupation
Not every 'AI engineer' title gets classified under the same Standard Occupational Classification code. Check your offer letter's job duties against the O*NET profile for Computer and Information Research Scientists or Software Developers to confirm the role qualifies before your employer files the LCA.
Ask your employer about E-Verify enrollment before your start date
H-1B1 visa holders are authorized to work only for the petitioning employer. Confirm your employer is enrolled in E-Verify and that your onboarding I-9 reflects your H-1B1 status accurately, since a mismatch at a STEM-heavy company can delay your first paycheck.
Request a two-year petition to align with your project runway
H-1B1 Chile status is granted in one-year increments at the consulate but your employer can structure the LCA for up to two years. Push for the longer period during offer negotiations so your work authorization doesn't expire mid-project.
Frequently Asked Questions
Does an AI ML Engineer role qualify as a specialty occupation for the H-1B1 Chile visa?
Yes. AI ML Engineer positions consistently require at least a bachelor's degree in computer science, mathematics, statistics, or a closely related field, which satisfies the H-1B1 visa specialty occupation standard. Your employer confirms this when certifying the Labor Condition Application with DOL. Roles that list a degree as preferred rather than required can create complications, so verify the job description reflects a degree requirement before your employer files.
How does the H-1B1 Chile visa compare to the H-1B for AI ML Engineer roles?
The H-1B1 Chile visa skips the H-1B lottery entirely and routes your application through the U.S. consulate in Chile rather than USCIS. The annual cap is 1,400 visas and has never been exhausted, meaning Chilean AI ML Engineers can apply at any time of year without waiting for an April registration window. The tradeoff is that H-1B visa1 does not confer dual intent, so maintaining nonimmigrant intent throughout the process matters.
How do I find employers who will sponsor an H-1B1 Chile visa for an AI ML Engineer position?
Migrate Mate is built specifically for this search. It surfaces AI ML Engineer job listings filtered by employers with H-1B1 Chile LCA filing history, so you're not cold-applying to companies that have never navigated the process. Employers already familiar with the consulate-based route move faster through the LCA certification and offer stage.
Can I start working while my H-1B1 Chile visa application is pending at the consulate?
No. Unlike an H-1B change of status filed with USCIS, the H-1B1 Chile process happens at the consulate, so you don't receive interim work authorization while your application is pending. You must have your visa stamp in hand before beginning employment with the sponsoring employer. Plan your start date around the consulate interview appointment window, not the LCA certification date.
What happens to my H-1B1 Chile status if my AI ML Engineer role changes significantly after I start?
Material changes to your job duties, worksite location, or employer require a new Labor Condition Application and, in most cases, a new H-1B1 visa stamp before the change takes effect. A promotion to engineering manager or a shift from model development to product strategy can constitute a material change. Your employer's immigration contact should review any role modification before it's finalized to avoid a status violation.