H-1B1 Singapore Visa Design Verification Jobs
Design Verification engineers from Singapore can pursue U.S. roles without entering an H-1B lottery. The H-1B1 Singapore visa's 5,400-visa annual cap rarely fills, and your employer files directly at the consulate rather than through USCIS. Sponsorship for chip validation and hardware verification roles is concentrated among semiconductor and EDA tool companies.
Find H-1B1 Singapore Visa Design Verification JobsOverview
Showing 5 of 70+ Design Verification jobs
See all 70+ Design Verification Jobs
Sign up for free to unlock all listings, filter by visa type, and get alerts for new Design Verification roles.
Get Access To All JobsSUMMARY
Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
DESCRIPTION
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Ensure bug-free first silicon for part of the SoC / IP and developing detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under care, execute verification plans, including design bring-up, DV environment bring-up, regression enabling all features under my care, and debug of the test failures. Develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.
PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
MINIMUM QUALIFICATIONS
- Master’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering or a related field.
- Experience and/or education must include:
- Utilizing System Verilog for constrained random verification and functional coverage.
- Utilizing UVM to develop verification environments and implement directed and random test cases.
- Utilizing C and C++ demonstrating strong software skills in data structures and algorithms.
- Utilizing Python and Perl for test vector generation and executable scripts.
- Utilizing EDA tools for testbench simulations, debugging, and coverage closure.
- Utilizing High-speed interface protocols for verifying high bandwidth, low power data communication systems.
- Utilizing Digital Design for understanding ASIC design flows and verification.
- Utilizing Computer Architecture for exploration of memory subsystem and architecture trade-off analysis.
PREFERRED QUALIFICATIONS
- N/A
This position is not subject to the application limits.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
Apple accepts applications to this posting on an ongoing basis.
SUMMARY
Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
DESCRIPTION
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Ensure bug-free first silicon for part of the SoC / IP and developing detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under care, execute verification plans, including design bring-up, DV environment bring-up, regression enabling all features under my care, and debug of the test failures. Develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.
PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
MINIMUM QUALIFICATIONS
- Master’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering or a related field.
- Experience and/or education must include:
- Utilizing System Verilog for constrained random verification and functional coverage.
- Utilizing UVM to develop verification environments and implement directed and random test cases.
- Utilizing C and C++ demonstrating strong software skills in data structures and algorithms.
- Utilizing Python and Perl for test vector generation and executable scripts.
- Utilizing EDA tools for testbench simulations, debugging, and coverage closure.
- Utilizing High-speed interface protocols for verifying high bandwidth, low power data communication systems.
- Utilizing Digital Design for understanding ASIC design flows and verification.
- Utilizing Computer Architecture for exploration of memory subsystem and architecture trade-off analysis.
PREFERRED QUALIFICATIONS
- N/A
This position is not subject to the application limits.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
Apple accepts applications to this posting on an ongoing basis.
See all 70+ H-1B1 Singapore Visa Design Verification Jobs
Sign up for free to unlock all listings, filter by visa type, and get alerts for new H-1B1 Singapore Visa Design Verification Jobs.
Get Access To All JobsTips for Finding Design Verification Jobs
Map your degree to SOC codes
Design Verification roles typically map to SOC 17-2061 (Electrical Engineers) or 15-1299 (Computer Hardware Engineers). Pull the O*NET profile for your target code before applying so your resume mirrors the specialty occupation language employers use in their LCA filings.
Filter employers by active LCA filings
Use Migrate Mate to identify companies with recent H-1B1 Singapore LCA filings for verification or validation roles. Employers who have filed before understand the consulate-only process and won't stall when you disclose your visa status.
Certify your Singapore degree equivalency early
U.S. employers sometimes question whether a three-year Singaporean bachelor's degree satisfies the specialty occupation requirement. Get a credential evaluation from a NACES-recognized evaluator before you start interviewing so you can provide it immediately if the hiring team or their immigration counsel asks.
Ask about DOL prevailing wage tier upfront
The H-1B1 visa requires your offered salary to meet the DOL prevailing wage for your role and location. Run the OFLC Wage Search for your target SOC code and metro area before offer negotiations so you can confirm the employer's package clears the threshold without delays during LCA filing.
Target companies already enrolled in E-Verify
Employers filing an LCA must attest to E-Verify compliance. Prioritize companies already enrolled, since those that aren't may need weeks to complete enrollment before they can file your LCA, pushing back your consulate appointment date.
Time your consulate appointment around tape-out cycles
Design Verification roles at semiconductor firms often go on hiring freezes during tape-out. Schedule your interview at the U.S. Embassy in Singapore at least six weeks before your intended start date so approval lands in a window when your team's workload allows for onboarding.
Frequently Asked Questions
Does Design Verification qualify as a specialty occupation for the H-1B1 Singapore visa?
Yes. Design Verification requires a bachelor's degree or higher in electrical engineering, computer engineering, or a closely related field, which meets the specialty occupation definition. Your employer confirms this in the Labor Condition Application filed with DOL. Roles involving RTL simulation, formal verification, or functional coverage analysis consistently meet the standard, but your degree field must align with the specific job duties your employer describes.
How does the H-1B1 Singapore visa differ from the H-1B for a Design Verification engineer?
The H-1B1 Singapore visa has no lottery and a rarely-filled annual cap of 5,400 visas, so you can apply any time of year rather than waiting for an April registration window. You apply at the U.S. Embassy in Singapore rather than waiting for USCIS to adjudicate a petition. The tradeoff is that H-1B1 does not grant dual intent, so maintaining clear nonimmigrant ties matters throughout your status.
How do I find employers actively sponsoring H-1B1 Singapore visas for verification roles?
Migrate Mate shows LCA filing history filtered by visa type and occupation, so you can identify semiconductor, EDA, and hardware companies that have sponsored Singaporean engineers in verification roles before. Targeting employers with an existing filing track record shortens the timeline significantly, since their legal teams already understand the consulate-only process and the DOL wage attestation requirements.
Can my employer file for H-1B1 Singapore sponsorship while I'm already in the U.S. on another visa?
Yes, but the H-1B1 visa is a consular visa, meaning you must apply at the U.S. Embassy in Singapore rather than change status from within the U.S. If you're currently on an F-1 or another nonimmigrant status, your employer can file the LCA and prepare the petition package, but you'll need to travel to Singapore to complete the consulate appointment before starting work under H-1B1.
What happens if my H-1B1 Singapore visa expires before my employer files a renewal?
The H-1B1 visa is granted in one-year increments and must be renewed annually at the consulate. Unlike H-1B, there is no USCIS-approved cap-gap extension. If your visa stamp lapses and you haven't completed your consulate renewal, you cannot legally continue working. Coordinate with your employer's immigration counsel to initiate the LCA re-certification and appointment scheduling at least eight weeks before your expiration date.