Design Verification Jobs for OPT Students
Design Verification engineers validate that hardware behaves as specified before tape-out, making this one of the most in-demand roles in semiconductor and chip design. Most positions require a bachelor's or master's in electrical engineering or computer engineering, which aligns well with STEM OPT's 36-month authorization window.
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Get Access To All JobsINTRODUCTION
At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI.
LOCATION:
Hybrid, working onsite at our Santa Clara office 3 days per week.
12 Week Program: June 1st - August 21st or June 22nd - September 11th
Job Title: HW Design Verification Intern
What you will do
You will work alongside a team building state-of-the-art LLM inference SoCs, gaining hands-on exposure to modern compute units, crossbars, chiplet interconnects, and high-performance memory interfaces.
In this role,
- You’ll contribute to the functional verification of complex hardware blocks using UVM-based methodologies and
- Accelerate bug-finding with formal verification techniques using SystemVerilog Assertions (SVA).
- You’ll also develop and maintain tools that improve simulation efficiency and verification productivity, and
- Help explore how emerging AI-assisted workflows can strengthen DV methodology.
What you will bring
- Pursuing a Master’s or PhD degree in Electrical and Computer Engineering, or a related scientific discipline
- Relevant coursework in Computer Architecture, Verilog, and/or FPGA development
- Familiarity with the SystemVerilog programming language (required)
- Familiarity with SystemVerilog Assertions (SVA) (preferred, not required)
- Current knowledge of AI SoC and/or LLM inference architectures (preferred, not required)
- Excellent verbal and written communication skills
Equal Opportunity Employment Policy
d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.
d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individuals interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of all applicants. Thank you for your understanding and cooperation.
INTRODUCTION
At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI.
LOCATION:
Hybrid, working onsite at our Santa Clara office 3 days per week.
12 Week Program: June 1st - August 21st or June 22nd - September 11th
Job Title: HW Design Verification Intern
What you will do
You will work alongside a team building state-of-the-art LLM inference SoCs, gaining hands-on exposure to modern compute units, crossbars, chiplet interconnects, and high-performance memory interfaces.
In this role,
- You’ll contribute to the functional verification of complex hardware blocks using UVM-based methodologies and
- Accelerate bug-finding with formal verification techniques using SystemVerilog Assertions (SVA).
- You’ll also develop and maintain tools that improve simulation efficiency and verification productivity, and
- Help explore how emerging AI-assisted workflows can strengthen DV methodology.
What you will bring
- Pursuing a Master’s or PhD degree in Electrical and Computer Engineering, or a related scientific discipline
- Relevant coursework in Computer Architecture, Verilog, and/or FPGA development
- Familiarity with the SystemVerilog programming language (required)
- Familiarity with SystemVerilog Assertions (SVA) (preferred, not required)
- Current knowledge of AI SoC and/or LLM inference architectures (preferred, not required)
- Excellent verbal and written communication skills
Equal Opportunity Employment Policy
d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.
d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individuals interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of all applicants. Thank you for your understanding and cooperation.
How to Get Visa Sponsorship in Design Verification
Target semiconductor-heavy hiring cycles
Semiconductor companies like Intel, Qualcomm, and AMD concentrate hiring in Q1 and Q3. Applying in these windows gives you the best chance of securing an offer before your OPT start date, leaving time for onboarding paperwork.
Confirm your role qualifies as STEM OPT
Design Verification falls under CIP code 14.1001 (Electrical and Electronics Engineering) for most EE and CE graduates. Confirm your degree CIP code with your DSO before accepting an offer to ensure your 24-month STEM extension is valid.
Lead with your verification methodology in applications
Employers screening OPT applicants move faster when they see UVM, SystemVerilog, or formal verification listed prominently. A methodology-first resume signals you can contribute from day one, which reduces perceived sponsorship risk for hiring managers.
Prioritize fabless and OSAT companies for H-1B sponsorship
Fabless semiconductor firms and outsourced assembly and test companies sponsor H-1B visas at high rates due to persistent engineering shortages. These employers are accustomed to the process and less likely to withdraw offers due to sponsorship concerns.
Document your verification contributions with metrics
Hiring managers at visa-sponsoring companies want evidence of impact. Quantify your work: coverage closure percentages, bugs caught pre-silicon, or simulation runtimes reduced. Concrete numbers make your case stronger during both hiring and any future H-1B petition.
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Get Access To All JobsFrequently Asked Questions
Do Design Verification roles qualify for the 24-month STEM OPT extension?
Yes, in most cases. Design Verification is rooted in electrical engineering or computer engineering, both of which appear on the STEM Designated Degree Program List. If your degree falls under a qualifying CIP code, your employer must sign a formal training plan (Form I-983) to activate the extension. Confirm your specific CIP code with your DSO before relying on STEM eligibility.
How do I find Design Verification employers who sponsor OPT and H-1B visas?
Migrate Mate filters job listings specifically for roles open to OPT and visa sponsorship, so you're not sorting through positions that exclude international candidates. Semiconductor companies filing Labor Condition Applications with the Department of Labor are publicly searchable and represent your strongest pool. Focus on companies with established hardware teams, as they have recurring verification headcount and sponsorship infrastructure already in place.
Can I work as a Design Verification contractor on OPT?
Yes, but there are constraints. OPT allows contract and consulting work as long as the role is directly related to your degree and you work at least 20 hours per week. For STEM OPT, your employer must be E-Verify enrolled and sign Form I-983, which some staffing firms and smaller contractors won't do. Verify E-Verify enrollment before accepting any contract offer.
What happens to my OPT status if my Design Verification role ends mid-authorization?
You enter a 60-day grace period the day your employment ends. During that window, you can search for a new qualifying role, transfer to a different visa status, or prepare to depart the U.S. You cannot work during the grace period. Unemployment also counts against your OPT authorization: post-completion OPT allows a maximum of 90 days of unemployment, and STEM OPT allows an additional 60 days.
Does working at a startup affect my STEM OPT eligibility as a Design Verification engineer?
It can. The employer must be enrolled in E-Verify, which many early-stage startups have not completed. If the startup is not E-Verify enrolled, it cannot legally employ you on STEM OPT, regardless of the role's technical nature. Ask the hiring manager directly before interviewing, and check E-Verify enrollment status on the DHS website. Established fabless startups with institutional backing are more likely to have compliance infrastructure in place.
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