R D Engineering Jobs in Sunnyvale, CA
R D Engineering jobs in Sunnyvale are concentrated in the Caribbean Drive corridor, the Lawrence Expressway tech belt, and the Mathilda Avenue innovation district, with strong demand across semiconductors, wireless communications, and advanced hardware development. Employers actively hiring include Synopsys, Nokia, and Solstice Advanced Materials. Scan the live roles below and apply to whichever ones fit.
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Showing 5 of 296+ R D Engineering jobs
Category Engineering Hire Type Employee Job ID 18881 Base Salary Range $230000-$344000 Remote Eligible No Date Posted 09/30/2026
- Define and drive corporate and customer-facing DFT methodologies for next-generation ASIC and SoC designs.
- Serve as a technical leader and subject matter expert for Synopsys TestMAX DFT, ATPG, diagnosis, and silicon lifecycle solutions.
- Lead deployment of advanced DFT architectures including scan compression, hierarchical DFT, boundary scan, IEEE 1500 wrapper solutions, IJTAG infrastructures, and embedded test technologies.
- Architect scalable test access and instrumentation networks leveraging IEEE 1149.1, IEEE 1149.6, IEEE 1687 (IJTAG), and IEEE 1500 standards.
- Develop best practices for DFT insertion, ATPG generation, pattern validation, diagnosis, and coverage optimization.
- Drive adoption of reusable methodologies, automation frameworks, and signoff criteria across multiple programs and business units.
- Collaborate with R&D organizations to influence future product capabilities and roadmap priorities.
- Provide technical leadership for strategic customer engagements, methodology reviews, and complex technical escalations.
- Mentor engineers across multiple teams and contribute to the development of the organization's DFT expertise.
- Enable successful deployment of industry-leading DFT methodologies across the world's most advanced semiconductor programs.
- Drive measurable improvements in test quality, manufacturability, and silicon reliability.
- Influence next-generation TestMAX capabilities through direct customer engagement and technical leadership.
- Accelerate adoption of advanced standards-based test architectures across strategic customer accounts.
- Improve engineering productivity through methodology standardization, automation, and best-practice development.
- Establish Synopsys as the trusted advisor and technology leader in DFT and manufacturing test solutions.
- Contribute to breakthrough technologies powering AI, automotive, networking, and high-performance computing applications.
- BS/MS in Electrical Engineering, Computer Engineering, or related field.
- 15+ years of experience in Semiconductor or EDA industry with a focus on DFT, ATPG, and manufacturing test methodologies.
- Demonstrated expertise in architecting and implementing DFT solutions for large-scale ASIC and SoC designs.
- Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions.
- Strong understanding of:
- Scan insertion and scan compression
- Hierarchical DFT methodologies
- ATPG and diagnosis
- Stuck-at, transition, path-delay, bridge, and cell-aware fault models
- Coverage analysis and optimization
- Test cost and pattern count reduction techniques
- Expertise with standards including:
- IEEE 1149.1 (JTAG)
- IEEE 1149.6 (AC JTAG)
- IEEE 1687 (IJTAG)
- IEEE 1500
- Experience developing and deploying:
- JTAG / TAP Architectures
- Boundary Scan Networks
- IJTAG Instrumentation Networks
- Embedded Instrument Access Solutions
- Expertise in deploying and integrating DFT IP including:
- Codec / Embedded Compression
- OCC (On-Chip Clock Controller)
- LBIST
- TAP Controllers
- JTAG and IJTAG Infrastructure
- TDR Networks
- IEEE 1500 Wrappers
- Strong understanding of RTL-to-GDSII implementation flows and interactions between DFT, synthesis, physical design, timing closure, and signoff.
- Proficiency with Tcl, Python, Perl, Shell, or similar scripting languages for methodology development and automation.
- Recognized expert in DFT architecture and test methodology deployment.
- Experience defining enterprise-wide DFT standards and signoff methodologies.
- Strong background supporting advanced-node ASICs and multi-billion gate SoCs.
- Experience with silicon bring-up, diagnosis, yield improvement, and production ramp.
- Knowledge of functional safety standards and test requirements for automotive applications.
- Experience collaborating directly with semiconductor customers in applications engineering, consulting, or methodology leadership roles.
- Contributions to industry test standards, technical publications, patents, or conference presentations are highly valued.
- A strategic technical leader capable of influencing engineering direction across organizations.
- A trusted advisor to customers, partners, and internal stakeholders.
- An exceptional communicator who can present complex technical concepts to diverse audiences.
- A mentor who develops talent and elevates the technical capabilities of those around them.
- An innovator who continuously seeks opportunities to improve methodologies, tools, and customer outcomes.
- Results-driven, highly collaborative, and passionate about solving the industry's most challenging DFT problems.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can
Category Engineering Hire Type Employee Job ID 18881 Base Salary Range $230000-$344000 Remote Eligible No Date Posted 09/30/2026
- Define and drive corporate and customer-facing DFT methodologies for next-generation ASIC and SoC designs.
- Serve as a technical leader and subject matter expert for Synopsys TestMAX DFT, ATPG, diagnosis, and silicon lifecycle solutions.
- Lead deployment of advanced DFT architectures including scan compression, hierarchical DFT, boundary scan, IEEE 1500 wrapper solutions, IJTAG infrastructures, and embedded test technologies.
- Architect scalable test access and instrumentation networks leveraging IEEE 1149.1, IEEE 1149.6, IEEE 1687 (IJTAG), and IEEE 1500 standards.
- Develop best practices for DFT insertion, ATPG generation, pattern validation, diagnosis, and coverage optimization.
- Drive adoption of reusable methodologies, automation frameworks, and signoff criteria across multiple programs and business units.
- Collaborate with R&D organizations to influence future product capabilities and roadmap priorities.
- Provide technical leadership for strategic customer engagements, methodology reviews, and complex technical escalations.
- Mentor engineers across multiple teams and contribute to the development of the organization's DFT expertise.
- Enable successful deployment of industry-leading DFT methodologies across the world's most advanced semiconductor programs.
- Drive measurable improvements in test quality, manufacturability, and silicon reliability.
- Influence next-generation TestMAX capabilities through direct customer engagement and technical leadership.
- Accelerate adoption of advanced standards-based test architectures across strategic customer accounts.
- Improve engineering productivity through methodology standardization, automation, and best-practice development.
- Establish Synopsys as the trusted advisor and technology leader in DFT and manufacturing test solutions.
- Contribute to breakthrough technologies powering AI, automotive, networking, and high-performance computing applications.
- BS/MS in Electrical Engineering, Computer Engineering, or related field.
- 15+ years of experience in Semiconductor or EDA industry with a focus on DFT, ATPG, and manufacturing test methodologies.
- Demonstrated expertise in architecting and implementing DFT solutions for large-scale ASIC and SoC designs.
- Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions.
- Strong understanding of:
- Scan insertion and scan compression
- Hierarchical DFT methodologies
- ATPG and diagnosis
- Stuck-at, transition, path-delay, bridge, and cell-aware fault models
- Coverage analysis and optimization
- Test cost and pattern count reduction techniques
- Expertise with standards including:
- IEEE 1149.1 (JTAG)
- IEEE 1149.6 (AC JTAG)
- IEEE 1687 (IJTAG)
- IEEE 1500
- Experience developing and deploying:
- JTAG / TAP Architectures
- Boundary Scan Networks
- IJTAG Instrumentation Networks
- Embedded Instrument Access Solutions
- Expertise in deploying and integrating DFT IP including:
- Codec / Embedded Compression
- OCC (On-Chip Clock Controller)
- LBIST
- TAP Controllers
- JTAG and IJTAG Infrastructure
- TDR Networks
- IEEE 1500 Wrappers
- Strong understanding of RTL-to-GDSII implementation flows and interactions between DFT, synthesis, physical design, timing closure, and signoff.
- Proficiency with Tcl, Python, Perl, Shell, or similar scripting languages for methodology development and automation.
- Recognized expert in DFT architecture and test methodology deployment.
- Experience defining enterprise-wide DFT standards and signoff methodologies.
- Strong background supporting advanced-node ASICs and multi-billion gate SoCs.
- Experience with silicon bring-up, diagnosis, yield improvement, and production ramp.
- Knowledge of functional safety standards and test requirements for automotive applications.
- Experience collaborating directly with semiconductor customers in applications engineering, consulting, or methodology leadership roles.
- Contributions to industry test standards, technical publications, patents, or conference presentations are highly valued.
- A strategic technical leader capable of influencing engineering direction across organizations.
- A trusted advisor to customers, partners, and internal stakeholders.
- An exceptional communicator who can present complex technical concepts to diverse audiences.
- A mentor who develops talent and elevates the technical capabilities of those around them.
- An innovator who continuously seeks opportunities to improve methodologies, tools, and customer outcomes.
- Results-driven, highly collaborative, and passionate about solving the industry's most challenging DFT problems.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can
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Find R D Engineering JobsR D Engineering Job Market in Sunnyvale
Who's Hiring
- Synopsys93
- Nokia78
- Solstice Advanced Materials47
- Matterport31
- CoStar16
Top Industries Hiring
- Telecommunications78
- Electronics & Hardware78
- Technology & Software31
- Medical Devices16
R D Engineering Jobs in Sunnyvale: Frequently Asked Questions
How do I get a r d engineering job in Sunnyvale?
Focus your search on Sunnyvale's dense semiconductor and wireless hardware ecosystem, where companies ranging from early-stage chipmakers to established systems integrators hire r d engineers year-round. Roles tend to cluster around the Lawrence Expressway corridor and the Peery Park area. Candidates who demonstrate hands-on lab experience, familiarity with RF or IC design workflows, and any previous internship with a Silicon Valley hardware firm consistently stand out in local hiring processes.
Which companies hire r d engineerings in Sunnyvale?
Companies currently hiring r d engineerings in Sunnyvale include Synopsys, Nokia, and Solstice Advanced Materials, per current listings on Migrate Mate as of October 2026. Sunnyvale's hiring base is especially deep in semiconductor IP, wireless chipsets, and defense electronics, drawing both large public companies and well-funded startups to the same talent pool.
Are there remote r d engineering jobs in Sunnyvale?
Yes, though r d engineering roles are less remote-friendly than purely analytical positions because much of the work involves lab equipment, prototypes, and hardware validation. About 14% of r d engineering openings tied to Sunnyvale are remote or hybrid as of October 2026, and those openings tend to be in simulation, firmware architecture, or technical documentation rather than hands-on device testing.
How can I get a r d engineering job in Sunnyvale with little or no experience?
The most realistic entry path in Sunnyvale is a junior or associate engineer role at one of the city's many mid-size semiconductor or wireless firms, which hire entry-level candidates who can demonstrate solid fundamentals in circuit design or signal processing. Sunnyvale employers also hire engineering interns who convert to full-time positions, and lateral moves from quality or test engineering into r d teams are common locally. A portfolio of academic projects, published coursework, or open-source hardware contributions gives candidates a concrete edge.
Which industries hire the most r d engineerings in Sunnyvale?
Most r d engineering openings in Sunnyvale sit in Telecommunications, Electronics & Hardware, and Technology & Software, per current listings on Migrate Mate as of October 2026. Sunnyvale's position at the center of Silicon Valley's semiconductor and communications supply chain means those sectors drive sustained hiring demand that holds up across economic cycles.
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