Senior Level RTL Design Engineer Jobs
Senior level rtl design engineer jobs place experienced engineers in charge of microarchitecture decisions, RTL ownership across complex SoC blocks, and the design reviews that shape what junior and mid-level engineers execute. Openings concentrate in Electronics & Hardware, Technology & Software, and Consulting & Professional Services, with a mix of on-site, remote, and hybrid roles available, and employers like Apple, Qualcomm, and Intel hiring at this level now.
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Showing 5 of 41+ Senior Level RTL Design Engineer jobs
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience with digital design using SystemVerilog RTL.
- Experience with power, performance and area optimizations.
Preferred qualifications:
- Experience interacting with software, architecture, physical design and other cross-functional teams.
- Knowledge of processor design, accelerators, or memory hierarchies.
About the job
As an ASIC Design Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $163000 - $237000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Work independently to create and review the compute subsystem's design microarchitecture specifications.
- Define compute subsystem integration requirements to the SOC.
- Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
- Work with design validation (DV) teams to create testplans to verify, and debug design RTL.
- Work with physical design teams to ensure design meets physical requirements and timing closure.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience with digital design using SystemVerilog RTL.
- Experience with power, performance and area optimizations.
Preferred qualifications:
- Experience interacting with software, architecture, physical design and other cross-functional teams.
- Knowledge of processor design, accelerators, or memory hierarchies.
About the job
As an ASIC Design Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $163000 - $237000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Work independently to create and review the compute subsystem's design microarchitecture specifications.
- Define compute subsystem integration requirements to the SOC.
- Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
- Work with design validation (DV) teams to create testplans to verify, and debug design RTL.
- Work with physical design teams to ensure design meets physical requirements and timing closure.
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Find JobsSenior Level RTL Design Engineer Job Market
Who's Hiring
- Apple14
- Qualcomm4
- Intel3
- Google3
- Broadcom2
Top Industries Hiring
- Electronics & Hardware27
- Technology & Software13
- Consulting & Professional Services5
- Telecommunications4
- Artificial Intelligence3
Senior Level RTL Design Engineer Jobs: Frequently Asked Questions
How do I get a senior level rtl design engineer job?
Employers hiring at the senior level expect demonstrated ownership of full RTL design flows, from specification through synthesis and timing closure, not just block-level contribution. Candidates who stand out can articulate microarchitecture trade-offs they drove, have experience with formal verification or low-power design techniques, and have mentored junior engineers through tape-out. A portfolio of shipped silicon carries more weight than any certification at this stage.
Which companies hire senior level rtl design engineers?
Companies hiring senior level rtl design engineers right now include Apple, Qualcomm, and Intel, based on current listings on Migrate Mate as of July 2026. Hiring at this level is led by semiconductor companies, fabless chip designers, and large technology firms building custom silicon for AI, networking, and consumer devices.
Are there remote senior level rtl design engineer jobs?
Yes, though most senior rtl design engineer roles still skew toward on-site or hybrid because of collaboration requirements around lab access, EDA tool infrastructure, and tape-out coordination. About 8% of senior level rtl design engineer openings are remote or hybrid as of July 2026, with fully remote roles most common at companies using cloud-based EDA environments.
What makes a rtl design engineer role senior level?
A senior rtl design engineer role is defined by scope and accountability rather than task execution. Senior engineers own blocks or subsystems end-to-end, make independent microarchitecture decisions, drive design reviews, and are responsible for meeting PPA targets. They are expected to mentor mid-level and junior engineers and to communicate trade-offs clearly to architects and program managers without supervision.
Which industries hire the most senior level rtl design engineers?
Senior Level rtl design engineer roles concentrate in Electronics & Hardware, Technology & Software, and Consulting & Professional Services, based on current listings on Migrate Mate as of July 2026. These sectors drive hiring because they are investing heavily in custom silicon development for AI accelerators, high-speed networking, and consumer SoCs, all of which require experienced engineers who can own complex RTL blocks through tape-out.