TN Visa Asic Verification Engineer Jobs
ASIC Verification Engineer roles qualify for TN visa sponsorship under the USMCA's engineer category, covering digital and mixed-signal verification work that requires a bachelor's degree in electrical engineering or computer engineering. Canadian citizens can apply at the port of entry with no cap; Mexican citizens require a consular visa appointment.
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Get Access To All JobsINTRODUCTION
The mission of the Instrumentation Division is to develop state-of-the-art instrumentation required for experimental research programs at Brookhaven Lab and to maintain the expertise and facilities in specialized high technology areas essential for this work. Development of facilities is motivated by present Brookhaven research programs and anticipated future directions of research. Our work has a significant impact on programs throughout the world that rely on state-of-the-art radiation detectors, readout electronics, data acquisition systems, and scientific instrumentation.
We seek a motivated Senior Digital ASIC Design Engineer to join our team as a senior digital designer for developing advanced readout ASICs and system-on-chip architectures for scientific instrumentation. The successful candidate will contribute to microelectronics for the Electron-Ion Collider (EIC), including ePIC detector systems, while also supporting ASICs for other programs in high-energy physics, nuclear physics, photon sciences, quantum information science, and related instrumentation efforts at BNL and with external partners.
In this role, you will lead the architecture, RTL design, implementation, and integration of digital blocks and subsystems for mixed-signal ASICs used in detector readout, trigger and timing distribution, data concentration, control, calibration, and high-speed data transmission. You will collaborate closely with analog and mixed-signal designers, verification engineers, physical design engineers, firmware developers, detector scientists, and other technical team members in the ASIC group, the Instrumentation Division, and the broader scientific community. We look for candidates with strong digital ASIC design expertise, particularly in low-power, radiation-aware, timing-critical, and data-intensive systems for scientific applications.
Our science and engineering challenges are complex and unique! We are engaged in the development of ASICs for particle detectors, high-resolution X- and gamma-ray spectrometers, high-rate photon counters and imagers, cryogenic and radiation-tolerant instrumentation, and other specialized systems for high-energy physics, nuclear physics, photon sciences, quantum information science, and related scientific programs. Our ASICs may operate in extreme environments, must meet stringent power, timing, noise, and radiation requirements, and must integrate reliably with sensors, FPGAs, data acquisition systems, and laboratory test infrastructure. The applications of these ASICs extend beyond BNL to national and international user facilities: your work will have the potential to shape the instruments used for scientific discovery and engineering advancements across the globe!
ESSENTIAL DUTIES AND RESPONSIBILITIES:
- Take a lead role in the architecture, microarchitecture, RTL design, and integration of digital ASICs and digital subsystems for scientific instruments, including EIC detector readout and related programs
- Develop design specifications based on detector, data acquisition, timing, power, radiation, and system integration requirements in conjunction with scientists, engineers, and project stakeholders
- Design and implement synthesizable RTL in SystemVerilog/Verilog for blocks such as data formatting, sparsification, buffering, trigger and timing interfaces, configuration and control, calibration logic, digital signal processing, and high-speed link interfaces
- Develop and maintain reusable digital IP, register maps, bus interfaces, clock and reset architectures, memory interfaces, finite-state machines, FIFOs, error detection/correction logic, and monitoring features suitable for ASIC integration
- Carry out or contribute to synthesis, static timing analysis, clock-domain crossing analysis, reset-domain crossing analysis, power estimation, linting, design-for-test insertion, and timing-driven physical implementation in Cadence, Synopsys, Siemens, or similar CAD/EDA environments
- Work closely with physical design and analog/mixed-signal teams to ensure successful floorplanning, partitioning, timing closure, power integrity, signal integrity, and mixed-signal integration
- Coordinate with verification engineers to define verification plans, develop self-checking test benches, review functional coverage, debug simulations, and close design issues before tapeout
- Support FPGA prototyping, laboratory evaluation, test-board development, bring-up, characterization, and integration of ASICs with sensors, firmware, and data acquisition systems
- Lead technical documentation, design reviews, interface control documents, and contributions to new project initiatives and proposals making use of emerging microelectronics technologies
REQUIRED KNOWLEDGE, SKILLS, AND ABILITIES:
- Bachelor's degree in electrical engineering, computer engineering, applied physics, or a closely related field of study
- Minimum seven (7) years of progressively responsible related work experience in digital ASIC design
- Demonstrated experience developing synthesizable RTL in SystemVerilog and/or Verilog for complex ASICs or system-on-chip designs
- Familiarity with ASIC design processes and flows, CAD/EDA tools for ASIC design, and their interoperability across design, verification, synthesis, timing, and physical implementation
- Experience with digital architecture, clocking and reset strategies, timing constraints, CDC/RDC methodology, low-power design considerations, and debugging of large digital systems
- Ability to work effectively with group members in a multi-user, process-design-kit-managed, version-controlled design environment and to step up to technical and schedule challenges
- Excellent written and oral communication skills, including the ability to document designs, participate in reviews, and work with multidisciplinary scientific and engineering teams
PREFERRED KNOWLEDGE, SKILLS, AND ABILITIES:
- Master's or Ph.D. in electrical engineering, computer engineering, applied physics, or a closely related field of study
- Experience with readout integrated circuits for radiation detectors, including detector timing, triggering, sparsified data readout, high-speed data transmission, calibration, and slow-control functions
- Experience with ASICs for particle physics, nuclear physics, photon sciences, cryogenic instrumentation, space or radiation environments, or other scientific applications
- Experience with digital implementation tools and flows such as synthesis, static timing analysis, formal equivalence checking, lint, CDC/RDC analysis, power analysis, DFT/scan, and automated place and route
- Familiarity with common on-chip bus and control interfaces such as AXI, AHB, APB, Wishbone, I2C, SPI, JTAG, and custom detector-readout protocols
- Experience with scripting and automation using Tcl, Python, Perl, Make, shell scripting, or similar tools in an EDA environment
- Knowledge of radiation-tolerant design techniques, single-event-effect mitigation, triple modular redundancy, error detection/correction, and design approaches for low-power or cryogenic operation
- Experience working with firmware, FPGA prototyping, board-level test systems, and laboratory characterization of ASICs
ADDITIONAL INFORMATION:
- This is a fully onsite position located at Brookhaven National Laboratory in Upton, NY.
Brookhaven National Laboratory is committed to providing fair, equitable and competitive compensation. The full salary range for this position is $115000 - $145000 / year. Salary offers will be commensurate with the final candidate’s qualification, education and experience and considered with the internal peer group.
Brookhaven National Laboratory is committed to employee success and we believe that a comprehensive employee benefits program is an important and meaningful part of the compensation employees receive. Review more information at BNL | Benefits Program
Brookhaven National Laboratory requires all non-badged personnel including visitors to produce a REAL-ID or REAL-ID compliant documentation to access Brookhaven National Laboratory – view more information at www.bnl.gov/real-id. This is due to nationwide identification requirements for federal site access as required by the federal REAL ID Act. Those not in possession of a REAL ID-compliant document will not be permitted to access the site which includes access to the Laboratory for interviews.
As a U.S. Department of Energy laboratory, Brookhaven National Laboratory requires employees to obtain and maintain a DOE Uncleared Personal Identity Verification (UPIV) credential in accordance with Homeland Security Presidential Directive 12 (HSPD-12) requirements. The credentialing process is completed as part of onboarding and enables access to DOE facilities and information systems. As a condition of employment, the selected candidate must be able to obtain and maintain a UPIV credential. These requirements are established under DOE Order 206.2 Chg. 2, Identity, Credential, and Access Management (ICAM- Identity, Credential, and Access Management (ICAM)), and DOE Order 473.1A- Physical Protection Program- Physical Protection Program.
About us
Brookhaven National Laboratory delivers discovery science and transformative technology to power and secure the nation’s future. Brookhaven Lab is a multidisciplinary laboratory with seven Nobel Prize-winning discoveries, 37 R&D 100 Awards, and more than 70 years of pioneering research. The Lab is primarily supported by the U.S. Department of Energy’s (DOE) Office of Science. Brookhaven Science Associates (BSA) operates and manages the Laboratory for DOE. BSA is a partnership between Battelle and The Research Foundation for the State University of New York on behalf of Stony Brook University. BSA salutes our veterans and active military members with careers that leverage the skills and unique experience they gained while serving our country.
EQUAL OPPORTUNITY/AFFIRMATIVE ACTION EMPLOYER
Guided by our core values of integrity, responsibility, innovation, respect, and teamwork, Brookhaven Science Associates is an Equal Employment Opportunity Employer-Vets/Disabled. We are committed to fostering a respectful and collaborative environment that fuels scientific discovery. We consider all qualified applicants without regard to any characteristic protected by law. All qualified individuals are encouraged to apply. We ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. *VEVRAA Federal Contractor
BSA employees are subject to restrictions related to participation in Foreign Government Talent Recruitment Programs, as defined and detailed in United States Department of Energy Order 486.1A. You will be asked to disclose any such participation at the time of hire for review by Brookhaven. The full text of the Order may be found at: https://www.directives.doe.gov/directives-documents/400-series/0486.1-BOrder-a/@@images/file
INTRODUCTION
The mission of the Instrumentation Division is to develop state-of-the-art instrumentation required for experimental research programs at Brookhaven Lab and to maintain the expertise and facilities in specialized high technology areas essential for this work. Development of facilities is motivated by present Brookhaven research programs and anticipated future directions of research. Our work has a significant impact on programs throughout the world that rely on state-of-the-art radiation detectors, readout electronics, data acquisition systems, and scientific instrumentation.
We seek a motivated Senior Digital ASIC Design Engineer to join our team as a senior digital designer for developing advanced readout ASICs and system-on-chip architectures for scientific instrumentation. The successful candidate will contribute to microelectronics for the Electron-Ion Collider (EIC), including ePIC detector systems, while also supporting ASICs for other programs in high-energy physics, nuclear physics, photon sciences, quantum information science, and related instrumentation efforts at BNL and with external partners.
In this role, you will lead the architecture, RTL design, implementation, and integration of digital blocks and subsystems for mixed-signal ASICs used in detector readout, trigger and timing distribution, data concentration, control, calibration, and high-speed data transmission. You will collaborate closely with analog and mixed-signal designers, verification engineers, physical design engineers, firmware developers, detector scientists, and other technical team members in the ASIC group, the Instrumentation Division, and the broader scientific community. We look for candidates with strong digital ASIC design expertise, particularly in low-power, radiation-aware, timing-critical, and data-intensive systems for scientific applications.
Our science and engineering challenges are complex and unique! We are engaged in the development of ASICs for particle detectors, high-resolution X- and gamma-ray spectrometers, high-rate photon counters and imagers, cryogenic and radiation-tolerant instrumentation, and other specialized systems for high-energy physics, nuclear physics, photon sciences, quantum information science, and related scientific programs. Our ASICs may operate in extreme environments, must meet stringent power, timing, noise, and radiation requirements, and must integrate reliably with sensors, FPGAs, data acquisition systems, and laboratory test infrastructure. The applications of these ASICs extend beyond BNL to national and international user facilities: your work will have the potential to shape the instruments used for scientific discovery and engineering advancements across the globe!
ESSENTIAL DUTIES AND RESPONSIBILITIES:
- Take a lead role in the architecture, microarchitecture, RTL design, and integration of digital ASICs and digital subsystems for scientific instruments, including EIC detector readout and related programs
- Develop design specifications based on detector, data acquisition, timing, power, radiation, and system integration requirements in conjunction with scientists, engineers, and project stakeholders
- Design and implement synthesizable RTL in SystemVerilog/Verilog for blocks such as data formatting, sparsification, buffering, trigger and timing interfaces, configuration and control, calibration logic, digital signal processing, and high-speed link interfaces
- Develop and maintain reusable digital IP, register maps, bus interfaces, clock and reset architectures, memory interfaces, finite-state machines, FIFOs, error detection/correction logic, and monitoring features suitable for ASIC integration
- Carry out or contribute to synthesis, static timing analysis, clock-domain crossing analysis, reset-domain crossing analysis, power estimation, linting, design-for-test insertion, and timing-driven physical implementation in Cadence, Synopsys, Siemens, or similar CAD/EDA environments
- Work closely with physical design and analog/mixed-signal teams to ensure successful floorplanning, partitioning, timing closure, power integrity, signal integrity, and mixed-signal integration
- Coordinate with verification engineers to define verification plans, develop self-checking test benches, review functional coverage, debug simulations, and close design issues before tapeout
- Support FPGA prototyping, laboratory evaluation, test-board development, bring-up, characterization, and integration of ASICs with sensors, firmware, and data acquisition systems
- Lead technical documentation, design reviews, interface control documents, and contributions to new project initiatives and proposals making use of emerging microelectronics technologies
REQUIRED KNOWLEDGE, SKILLS, AND ABILITIES:
- Bachelor's degree in electrical engineering, computer engineering, applied physics, or a closely related field of study
- Minimum seven (7) years of progressively responsible related work experience in digital ASIC design
- Demonstrated experience developing synthesizable RTL in SystemVerilog and/or Verilog for complex ASICs or system-on-chip designs
- Familiarity with ASIC design processes and flows, CAD/EDA tools for ASIC design, and their interoperability across design, verification, synthesis, timing, and physical implementation
- Experience with digital architecture, clocking and reset strategies, timing constraints, CDC/RDC methodology, low-power design considerations, and debugging of large digital systems
- Ability to work effectively with group members in a multi-user, process-design-kit-managed, version-controlled design environment and to step up to technical and schedule challenges
- Excellent written and oral communication skills, including the ability to document designs, participate in reviews, and work with multidisciplinary scientific and engineering teams
PREFERRED KNOWLEDGE, SKILLS, AND ABILITIES:
- Master's or Ph.D. in electrical engineering, computer engineering, applied physics, or a closely related field of study
- Experience with readout integrated circuits for radiation detectors, including detector timing, triggering, sparsified data readout, high-speed data transmission, calibration, and slow-control functions
- Experience with ASICs for particle physics, nuclear physics, photon sciences, cryogenic instrumentation, space or radiation environments, or other scientific applications
- Experience with digital implementation tools and flows such as synthesis, static timing analysis, formal equivalence checking, lint, CDC/RDC analysis, power analysis, DFT/scan, and automated place and route
- Familiarity with common on-chip bus and control interfaces such as AXI, AHB, APB, Wishbone, I2C, SPI, JTAG, and custom detector-readout protocols
- Experience with scripting and automation using Tcl, Python, Perl, Make, shell scripting, or similar tools in an EDA environment
- Knowledge of radiation-tolerant design techniques, single-event-effect mitigation, triple modular redundancy, error detection/correction, and design approaches for low-power or cryogenic operation
- Experience working with firmware, FPGA prototyping, board-level test systems, and laboratory characterization of ASICs
ADDITIONAL INFORMATION:
- This is a fully onsite position located at Brookhaven National Laboratory in Upton, NY.
Brookhaven National Laboratory is committed to providing fair, equitable and competitive compensation. The full salary range for this position is $115000 - $145000 / year. Salary offers will be commensurate with the final candidate’s qualification, education and experience and considered with the internal peer group.
Brookhaven National Laboratory is committed to employee success and we believe that a comprehensive employee benefits program is an important and meaningful part of the compensation employees receive. Review more information at BNL | Benefits Program
Brookhaven National Laboratory requires all non-badged personnel including visitors to produce a REAL-ID or REAL-ID compliant documentation to access Brookhaven National Laboratory – view more information at www.bnl.gov/real-id. This is due to nationwide identification requirements for federal site access as required by the federal REAL ID Act. Those not in possession of a REAL ID-compliant document will not be permitted to access the site which includes access to the Laboratory for interviews.
As a U.S. Department of Energy laboratory, Brookhaven National Laboratory requires employees to obtain and maintain a DOE Uncleared Personal Identity Verification (UPIV) credential in accordance with Homeland Security Presidential Directive 12 (HSPD-12) requirements. The credentialing process is completed as part of onboarding and enables access to DOE facilities and information systems. As a condition of employment, the selected candidate must be able to obtain and maintain a UPIV credential. These requirements are established under DOE Order 206.2 Chg. 2, Identity, Credential, and Access Management (ICAM- Identity, Credential, and Access Management (ICAM)), and DOE Order 473.1A- Physical Protection Program- Physical Protection Program.
About us
Brookhaven National Laboratory delivers discovery science and transformative technology to power and secure the nation’s future. Brookhaven Lab is a multidisciplinary laboratory with seven Nobel Prize-winning discoveries, 37 R&D 100 Awards, and more than 70 years of pioneering research. The Lab is primarily supported by the U.S. Department of Energy’s (DOE) Office of Science. Brookhaven Science Associates (BSA) operates and manages the Laboratory for DOE. BSA is a partnership between Battelle and The Research Foundation for the State University of New York on behalf of Stony Brook University. BSA salutes our veterans and active military members with careers that leverage the skills and unique experience they gained while serving our country.
EQUAL OPPORTUNITY/AFFIRMATIVE ACTION EMPLOYER
Guided by our core values of integrity, responsibility, innovation, respect, and teamwork, Brookhaven Science Associates is an Equal Employment Opportunity Employer-Vets/Disabled. We are committed to fostering a respectful and collaborative environment that fuels scientific discovery. We consider all qualified applicants without regard to any characteristic protected by law. All qualified individuals are encouraged to apply. We ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. *VEVRAA Federal Contractor
BSA employees are subject to restrictions related to participation in Foreign Government Talent Recruitment Programs, as defined and detailed in United States Department of Energy Order 486.1A. You will be asked to disclose any such participation at the time of hire for review by Brookhaven. The full text of the Order may be found at: https://www.directives.doe.gov/directives-documents/400-series/0486.1-BOrder-a/@@images/file
See all 78+ TN Visa Asic Verification Engineer Jobs
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Get Access To All JobsTips for Finding TN Visa Sponsorship as an Asic Verification Engineer
Align your credentials to TN engineer requirements
Your degree title matters at the border. A diploma in electrical engineering or computer engineering maps cleanly to the TN visa engineer category. A computer science degree can qualify, but be ready to show how your coursework directly supports verification engineering work.
Target employers with recent visa filing experience
Semiconductor companies with recent visa filings for engineering roles have experience navigating work visa sponsorship processes. Prioritize fabless chip designers, EDA vendors, and automotive IC teams, where ASIC verification positions align with typical sponsorship patterns and recurring hiring needs.
Clarify the support letter scope before accepting an offer
The employer support letter must specify your role as an engineer, your degree field, and that the position requires theoretical and practical application of engineering principles. A vague letter listing only job duties without connecting to the TN engineer definition gets questioned at the port of entry.
Search for TN-ready roles using Migrate Mate
Filter by TN visa eligibility and engineering job codes on Migrate Mate to surface ASIC and RTL verification openings at companies already familiar with the TN process, cutting time spent educating recruiters from scratch.
Prepare for Mexican nationals' consular appointment timeline
Mexican citizens apply through a U.S. consulate rather than at the port of entry. Consular appointment availability varies by location and season. Build at least four to six weeks into your start date negotiation to account for scheduling and administrative processing.
Document your tool and methodology expertise for CBP review
CBP officers assess whether your role genuinely requires an engineering degree. Bring documentation showing your work with UVM, SystemVerilog, formal verification tools, or coverage closure methodologies. This evidence ties your daily work to specialized engineering knowledge rather than general software tasks.
Asic Verification Engineer TN Visa: Frequently Asked Questions
Does an ASIC Verification Engineer role qualify for a TN visa?
Yes. ASIC Verification Engineer roles qualify under the TN engineer category when the position requires a bachelor's degree or higher in electrical engineering, computer engineering, or a closely related field. The role must involve theoretical and practical application of engineering principles. Positions focused exclusively on scripting or test execution without engineering analysis may face additional scrutiny from CBP.
How does the TN visa compare to H-1B for ASIC Verification Engineers?
The TN visa has no annual lottery, no cap for Canadian citizens, and can be approved at the port of entry the same day for Canadians. H-1B visa requires employer sponsorship through a lottery with a March registration window and typically a six-month wait. For Canadian ASIC engineers, TN is substantially faster and more predictable. Mexican nationals face a consular process but still avoid the H-1B lottery entirely.
Can a computer science degree support a TN ASIC Verification Engineer application?
It can, but requires more preparation than an electrical or computer engineering degree. You'll need to demonstrate that your coursework and professional experience involve engineering analysis, not just programming or software development. A detailed employer support letter that explicitly connects your CS background to the engineering functions of the verification role strengthens the application significantly.
Where can I find ASIC Verification Engineer jobs that offer TN visa sponsorship?
Migrate Mate is built specifically for TN visa job seekers. You can filter openings by TN eligibility and engineering job codes to find companies that actively sponsor TN visas for hardware and verification roles, rather than applying broadly and discovering late in the process that a company doesn't support TN sponsorship.
What happens to my TN status if my ASIC Verification Engineer role changes significantly?
If your responsibilities shift substantially, for example moving from RTL verification to a program management function, your existing TN approval may no longer accurately describe your role. You'd need to obtain a new TN reflecting the updated job duties. Continuing in a materially different role under an outdated TN approval creates compliance risk for both you and your employer.