Design Engineer Visa Sponsorship Jobs in California
Design engineer visa sponsorship jobs in California are concentrated in Silicon Valley, San Francisco, and San Diego, where companies like Apple, Google, and Qualcomm regularly hire international engineering talent. The state's semiconductor, aerospace, and consumer electronics industries create steady demand for design engineers across hardware, VLSI, and embedded systems disciplines.
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Get Access To All JobsLOCATION: Fully onsite in San Jose CA
JOB DUTIES:
You will build behavioral models of analog and mixed-signal circuits (PLLs, clocking, ADC/DAC, TX/RX analog front ends, calibration loops) in SystemVerilog. Those models drop into a SystemVerilog UVM verification environment used for high-speed SerDes and SoC IP. You will work closely with analog circuit designers, RTL designers and verification engineers. Successful candidates will be responsible for leading, and participating in, the modeling and verification of leading-edge designs in advanced CMOS processes.
Our modeling engineers are expected to contribute in all of the following areas:
- Reading schematics, netlists and circuit specifications to define what each model must capture
- Developing model architecture and accuracy targets, balancing fidelity against simulation speed
- Writing behavioral SystemVerilog models of analog blocks
- Validating models against transistor-level simulation results
- Debugging simulation failures and finding the root cause in the model, RTL or testbench
- Documenting model behavior, limitations and interfaces
EXPERIENCE AND EDUCATION:
Hands-on experience writing behavioral models of analog circuits in SystemVerilog. Working knowledge of analog and mixed-signal circuit fundamentals and of the SystemVerilog UVM methodology, with proven skill debugging failures in simulation and waveforms. Familiarity with high-speed interface standards is a plus.
Notes:
Looking for a candidate with RTL coding experience but also Analog Design/Modeling experience.
Would like to see experience with VCS and LTSPICE and HSPICE simulation.
VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status.
LOCATION: Fully onsite in San Jose CA
JOB DUTIES:
You will build behavioral models of analog and mixed-signal circuits (PLLs, clocking, ADC/DAC, TX/RX analog front ends, calibration loops) in SystemVerilog. Those models drop into a SystemVerilog UVM verification environment used for high-speed SerDes and SoC IP. You will work closely with analog circuit designers, RTL designers and verification engineers. Successful candidates will be responsible for leading, and participating in, the modeling and verification of leading-edge designs in advanced CMOS processes.
Our modeling engineers are expected to contribute in all of the following areas:
- Reading schematics, netlists and circuit specifications to define what each model must capture
- Developing model architecture and accuracy targets, balancing fidelity against simulation speed
- Writing behavioral SystemVerilog models of analog blocks
- Validating models against transistor-level simulation results
- Debugging simulation failures and finding the root cause in the model, RTL or testbench
- Documenting model behavior, limitations and interfaces
EXPERIENCE AND EDUCATION:
Hands-on experience writing behavioral models of analog circuits in SystemVerilog. Working knowledge of analog and mixed-signal circuit fundamentals and of the SystemVerilog UVM methodology, with proven skill debugging failures in simulation and waveforms. Familiarity with high-speed interface standards is a plus.
Notes:
Looking for a candidate with RTL coding experience but also Analog Design/Modeling experience.
Would like to see experience with VCS and LTSPICE and HSPICE simulation.
VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status.
Design Engineer Job Roles in California
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Search Design Engineer Jobs in CaliforniaDesign Engineer Jobs in California: Frequently Asked Questions
Which companies sponsor visas for design engineers in California?
California's largest design engineer visa sponsors include Apple, Qualcomm, Intel, NVIDIA, Broadcom, and Google. Aerospace employers like Northrop Grumman and Lockheed Martin also file regularly for design engineering roles, particularly in Southern California. Semiconductor and fabless chip companies concentrated in Silicon Valley and San Diego consistently appear in Department of Labor LCA disclosure data for this occupation.
Which visa types are most common for design engineer roles in California?
The H-1B visa is the most common visa for design engineers in California, as most roles require a bachelor's degree or higher in electrical engineering, mechanical engineering, or a related field, qualifying them as specialty occupations. Australians may pursue the E-3 visa as an H-1B alternative. Senior engineers with distinguished records sometimes qualify for the O-1A. Canadian and Mexican nationals may be eligible for TN visa status under the engineer category.
Which cities in California have the most design engineer sponsorship jobs?
San Jose and the broader Silicon Valley corridor lead for hardware and VLSI design engineer roles, driven by the semiconductor cluster there. San Francisco and the East Bay add software-integrated design positions. San Diego is a major hub for RF, mixed-signal, and wireless chip design, anchored by Qualcomm. Los Angeles and Orange County offer aerospace and defense design engineering opportunities through employers like Northrop Grumman and Raytheon.
How to find design engineer visa sponsorship jobs in California?
Migrate Mate filters design engineer jobs in California specifically by visa sponsorship availability, saving you from sorting through postings that won't support international candidates. You can search by city, discipline, and employer to focus on companies with a track record of sponsoring design engineers. Filtering by role type, such as hardware, mechanical, or embedded systems, helps narrow results to positions matching your engineering background.
Are there state-specific considerations for design engineers pursuing sponsorship in California?
California's Department of Industrial Relations sets prevailing wage determinations independently for some regulated occupations, and California-based employers must also comply with strict state labor laws alongside federal LCA wage requirements. Many California design engineering employers, particularly in semiconductors and defense, require security clearances that are unavailable to most nonimmigrant visa holders, which narrows the sponsoring employer pool in those sectors. University programs at UC Berkeley, Stanford, and UCLA feed a strong local talent pipeline, so international candidates benefit from emphasizing specialized technical skills.
What is the prevailing wage for sponsored design engineer jobs in California?
U.S. employers sponsoring a visa must pay at least the prevailing wage, which is what workers in the same role, area, and experience level typically earn. The Department of Labor sets this rate to make sure companies aren't hiring foreign workers simply because they'd accept lower pay than a U.S. worker. It varies by job title, location, and experience. You can look up current prevailing wage rates for any occupation and location using the OFLC Wage Search page.