Green Card Senior Physical Design Engineer Jobs
Senior Physical Design Engineer roles qualify for EB-2 and EB-3 green card sponsorship through the PERM labor certification process, which requires employers to document recruitment efforts before filing an I-140 immigrant petition. Semiconductor and chip design companies regularly sponsor foreign professionals in this role, making it one of the stronger pathways to permanent residency in the hardware engineering field.
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Get Access To All JobsINTRODUCTION
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As an SoC Physical Design Senior Manager, HBM in the Heterogeneous Integration Group (HIG), you will lead a team of physical design and physical verification engineers responsible for implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tapeout. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations.
Key Responsibilities
- Recruit, develop, and mentor a team of physical design engineers delivering HBM base die products.
- Plan project resourcing requirements and timelines. Prioritize resources across projects and individual assignments to meet aggressive product delivery schedules.
- Drive physical implementation for SoC blocks and/or top-level including floorplanning, placement, CTS, routing, and physical optimization to meet PPA targets.
- Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
- Collaborate with design and integration teams to ensure clean implementation of clocking/reset strategy, power architecture, and SoC integration requirements.
- Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY-adjacent logic) with focus on robust physical integration and timing/power integrity.
- Perform and/or coordinate physical signoff including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
- Support tapeout execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
- Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.
- Drive agentic AI development initiatives and develop AI/LLM driven workflows.
BASIC QUALIFICATIONS
- Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
- Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
- Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
- Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
- Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
- Exposure to hierarchical physical design, top-level assembly, partitioning guidelines, and large-scale integration methodology.
- Knowledge of IR/EM analysis, noise, coupling/crosstalk considerations, and mitigation strategies.
- Proven tapeout history on advanced foundries (e.g., TSMC) and understanding of full-cycle SoC development flows.
- Ability to work in a global, cross-functional environment with strong communication and debugging skills.
- Experience implementing AI flows and using agentic AI and LLMs.
PREFERRED QUALIFICATIONS
- Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum 15 years of experience in a related field.
- Proven ability to mentor and develop junior engineers.
COMPENSATION
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$177,000.00 - $309,000.00 a year
Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn about your right to work click here.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
INTRODUCTION
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As an SoC Physical Design Senior Manager, HBM in the Heterogeneous Integration Group (HIG), you will lead a team of physical design and physical verification engineers responsible for implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tapeout. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations.
Key Responsibilities
- Recruit, develop, and mentor a team of physical design engineers delivering HBM base die products.
- Plan project resourcing requirements and timelines. Prioritize resources across projects and individual assignments to meet aggressive product delivery schedules.
- Drive physical implementation for SoC blocks and/or top-level including floorplanning, placement, CTS, routing, and physical optimization to meet PPA targets.
- Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
- Collaborate with design and integration teams to ensure clean implementation of clocking/reset strategy, power architecture, and SoC integration requirements.
- Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY-adjacent logic) with focus on robust physical integration and timing/power integrity.
- Perform and/or coordinate physical signoff including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
- Support tapeout execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
- Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.
- Drive agentic AI development initiatives and develop AI/LLM driven workflows.
BASIC QUALIFICATIONS
- Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
- Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
- Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
- Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
- Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
- Exposure to hierarchical physical design, top-level assembly, partitioning guidelines, and large-scale integration methodology.
- Knowledge of IR/EM analysis, noise, coupling/crosstalk considerations, and mitigation strategies.
- Proven tapeout history on advanced foundries (e.g., TSMC) and understanding of full-cycle SoC development flows.
- Ability to work in a global, cross-functional environment with strong communication and debugging skills.
- Experience implementing AI flows and using agentic AI and LLMs.
PREFERRED QUALIFICATIONS
- Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum 15 years of experience in a related field.
- Proven ability to mentor and develop junior engineers.
COMPENSATION
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$177,000.00 - $309,000.00 a year
Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn about your right to work click here.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
See all 187+ Green Card Senior Physical Design Engineer Jobs
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Get Access To All JobsTips for Finding Green Card Sponsorship as a Senior Physical Design Engineer
Translate your PD skills into PERM language
Your tape-out experience, floorplanning work, and timing closure skills map to specific DOL job duty language. Align your resume to the exact duties your employer will list on the PERM application to avoid labor certification delays from mismatched documentation.
Target fabless and IDM companies with PERM history
Search OFLC PERM disclosure data for employers who have certified physical design or VLSI engineering roles in the past two years. Companies that have done it before understand the process and are less likely to abandon sponsorship midway.
Verify your EB-2 eligibility before accepting EB-3 offers
If you hold a master's degree in electrical engineering or a related field, push for EB-2 classification. EB-2 priority dates move faster for most countries, and the advanced-degree requirement is straightforward for most Senior Physical Design Engineer candidates.
Check prevailing wage before negotiating your offer
Use the OFLC Wage Search to look up the Level III or Level IV prevailing wage for your SOC code and work location before salary discussions. Your employer's PERM application must certify wages at or above this threshold, so understanding it protects you in negotiations.
Find green-card-sponsoring employers through Migrate Mate
Use Migrate Mate to search for Senior Physical Design Engineer roles filtered by green card sponsorship history. The platform surfaces employers with active EB-2 and EB-3 filing records so you're applying to companies already set up to run the PERM process.
Ask your employer about concurrent I-140 and I-485 filing
Once the PERM is certified and your priority date is current, USCIS allows concurrent filing of the I-140 petition and the I-485 adjustment of status application. This can shorten total processing time significantly for candidates in countries without severe backlog issues.
Green Card Senior Physical Design Engineer: Frequently Asked Questions
Do Senior Physical Design Engineer roles commonly qualify for EB-2 or EB-3 green card sponsorship?
Both categories apply. EB-2 covers candidates with a master's degree or higher in electrical engineering, computer engineering, or a closely related field, which describes most senior-level physical design hires. EB-3 covers professionals with a relevant bachelor's degree. Employers in the semiconductor industry routinely sponsor both categories because the role meets the specialty occupation and advanced-degree requirements under PERM labor certification rules.
How does green card sponsorship differ from H-1B sponsorship for this role?
H-1B visa is a temporary nonimmigrant status capped at 85,000 new approvals annually, requiring a lottery for most applicants and lasting a maximum of six years without an approved I-140. EB-2 and EB-3 green card sponsorship through PERM leads to permanent residency with no annual cap on petitions filed. The tradeoff is timeline: PERM labor certification alone takes six months to over a year before the I-140 stage begins, making early employer conversations essential.
What does the PERM labor certification process require from a Senior Physical Design Engineer candidate?
The employer drives the PERM filing, but you need to meet the minimum requirements documented in the job description exactly as written. Any credential gaps, such as a degree in a tangentially related field or experience that doesn't match the stated duties, can trigger a DOL audit. Before your employer files, review the ETA-9089 job description carefully and confirm your qualifications align with every listed requirement.
How can I find Senior Physical Design Engineer jobs where the employer already sponsors green cards?
Use Migrate Mate to filter Senior Physical Design Engineer roles by green card sponsorship history. This surfaces companies that have already completed PERM certifications for similar positions, which is a reliable indicator that they have internal HR processes and immigration counsel in place. Applying to companies with no prior PERM history often means educating them on the process during your job search, which adds risk and delay.
Does country of birth affect my green card timeline as a Senior Physical Design Engineer?
Yes. If you were born in India or China, EB-2 and EB-3 priority date backlogs can extend wait times by years beyond the PERM and I-140 stages due to per-country annual limits on immigrant visa numbers. Candidates born in other countries face significantly shorter waits. Reviewing the USCIS Visa Bulletin monthly helps you track your priority date and plan status maintenance, such as H-1B extensions under AC21 portability rules.