Remote Layout Design Engineer Jobs
Remote Layout Design Engineer jobs are open across the U.S. in sectors like semiconductor design, aerospace, automotive electronics, and consumer hardware, where distributed engineering teams have made remote layout work standard practice. Companies actively hiring remotely right now include Amrize, Impinj, and Infotron. Scan the live roles below and apply to whichever ones fit.
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See related jobsINTRODUCTION
Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. As we scale rapidly, we are looking for a driven and resourceful High-Speed Analog Layout Engineer to be the backbone of our daily operations and a key partner in shaping our company culture.
We are seeking a Principal/Senior Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits. You will interface closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success. This is a hands-on technical role ideal for someone who thrives in a fast-paced environment and enjoys mentoring others while contributing directly to cutting-edge chip development.
ROLE AND RESPONSIBILITIES
- Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
- Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability
- Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification
- Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.)
- Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing
- Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence
- Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus)
BASIC QUALIFICATIONS
- Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies
- Proven track record of top level integration IP layout macros and preparing IPs for handoff to Physical Design
- Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred)
- At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16)
- Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance
- Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
- Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
- Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools
- Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules
- Experience working in collaborative environments with international and remote teams
- Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams
- Experience using revision control systems for layout design management
PREFERRED QUALIFICATIONS
- Exposure to optical or high-speed analog interfaces is a strong plus
- Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization
- Proven ability to collaborate with international teams (U.S., Canada, Argentina)
- Strong organizational skills with high attention to detail and follow-through
- Ability to multi-task and prioritize in a fast-paced, dynamic environment
- Proactive, eager-to-learn mindset with excellent problem-solving skills
WHAT WE OFFER
- The chance to play a foundational role at a high-growth semiconductor start-up
- Exposure to a wide variety of cross functional teams
- A collaborative, international team culture where ideas and initiative are valued
- The opportunity to grow alongside Celero as we scale and shape the future of our industry
- A foundational role at a fast-growing semiconductor start-up shaping the future of AI and data center connectivity
INTRODUCTION
Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. As we scale rapidly, we are looking for a driven and resourceful High-Speed Analog Layout Engineer to be the backbone of our daily operations and a key partner in shaping our company culture.
We are seeking a Principal/Senior Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits. You will interface closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success. This is a hands-on technical role ideal for someone who thrives in a fast-paced environment and enjoys mentoring others while contributing directly to cutting-edge chip development.
ROLE AND RESPONSIBILITIES
- Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
- Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability
- Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification
- Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.)
- Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing
- Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence
- Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus)
BASIC QUALIFICATIONS
- Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies
- Proven track record of top level integration IP layout macros and preparing IPs for handoff to Physical Design
- Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred)
- At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16)
- Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance
- Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
- Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
- Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools
- Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules
- Experience working in collaborative environments with international and remote teams
- Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams
- Experience using revision control systems for layout design management
PREFERRED QUALIFICATIONS
- Exposure to optical or high-speed analog interfaces is a strong plus
- Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization
- Proven ability to collaborate with international teams (U.S., Canada, Argentina)
- Strong organizational skills with high attention to detail and follow-through
- Ability to multi-task and prioritize in a fast-paced, dynamic environment
- Proactive, eager-to-learn mindset with excellent problem-solving skills
WHAT WE OFFER
- The chance to play a foundational role at a high-growth semiconductor start-up
- Exposure to a wide variety of cross functional teams
- A collaborative, international team culture where ideas and initiative are valued
- The opportunity to grow alongside Celero as we scale and shape the future of our industry
- A foundational role at a fast-growing semiconductor start-up shaping the future of AI and data center connectivity
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Find JobsRemote Layout Design Engineer Job Market
Who's Hiring
What Employers Look For
The qualifications that appear most often in remote layout design engineer jobs.
- Proficiency in Cadence Virtuoso or equivalent EDA layout tools
- Experience with DRC, LVS, and parasitic extraction sign-off flows
- Hands-on work with CMOS process nodes at 28nm or below
- Understanding of analog, RF, or mixed-signal layout techniques
- Bachelor's degree in electrical engineering or a closely related field
- Familiarity with foundry design rule manuals and PDK usage
Tips for Your Remote Layout Design Engineer Job Search
Show async collaboration skills in your portfolio
Remote layout teams depend on shared PDKs, version-controlled design files, and written review cycles. Include design files or documentation that show you can hand off clean work, respond to DRC feedback in writing, and move a layout from schematic to sign-off without in-person check-ins.
Apply early to remote roles that fit
Migrate Mate lists remote layout design engineer openings from companies across the U.S. in one place, so you can find roles that match your tool stack and seniority and apply directly without sorting through unrelated postings.
Target companies with distributed engineering teams
Fabless semiconductor startups, aerospace defense contractors, and consumer electronics firms with no single headquarters are the most consistent sources of fully remote layout roles. Focus your search on companies where distributed engineering is structural, not an exception granted to individual employees.
Prove tool proficiency before the screening call
Remote employers can't watch you work, so they weight verifiable credentials heavily. Cloud-based EDA certifications, completed Cadence or Mentor training modules, and screenshots of clean DRC and LVS reports all give hiring managers concrete evidence before a first interview.
Remote Layout Design Engineer Jobs: Frequently Asked Questions
How do I get a remote layout design engineer job?
Remote layout design engineer roles go to candidates who can demonstrate independent execution from day one. Hiring managers at distributed teams screen for proficiency in tools like Cadence Virtuoso, Allegro, or Mentor Graphics, strong async written communication, and the ability to interpret specifications and iterate without in-person handoffs. A portfolio of completed layout projects, ideally with DRC and LVS sign-off documentation, sets candidates apart from applicants who list skills without proof.
Which companies hire remote layout design engineers?
Remote layout design engineer roles are posted by Amrize, Impinj, and Infotron and others right now, based on current remote listings on Migrate Mate as of November 2026. These include remote-first semiconductor firms, distributed aerospace and defense contractors, and consumer electronics companies that have built fully distributed IC and PCB layout teams.
Can you get a remote layout design engineer job with no experience?
Yes, but remote entry-level layout design engineer roles are harder to land because you must demonstrate self-sufficiency before employers can observe your work in person. Smaller fabless semiconductor startups and EDA training companies occasionally hire junior layout designers remotely. A candidate can substitute experience with completed personal or academic layout projects, verified clean DRC runs, and familiarity with remote collaboration workflows like shared PDKs and version-controlled design files.
Do you need a degree for remote layout design engineer jobs?
Not always. Many remote layout design engineer postings list a degree in electrical engineering or a related field as preferred, not required. Remote employers weigh demonstrated tool proficiency, a verifiable project portfolio showing clean layout results, and the ability to work independently against tapeout checklists. Candidates who can show completed physical designs with sign-off documentation often compete effectively regardless of formal credentials.
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