Layout Design Engineer Jobs
Layout Design Engineer jobs are open across semiconductor, aerospace, automotive, and consumer electronics industries, from entry-level to principal and staff, with specializations in analog, mixed-signal, and digital IC layout. Scan the live roles below and apply to whichever ones fit.
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INTRODUCTION
Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. As we scale rapidly, we are looking for a driven and resourceful High-Speed Analog Layout Engineer to be the backbone of our daily operations and a key partner in shaping our company culture.
We are seeking a Principal/Senior Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits. You will interface closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success. This is a hands-on technical role ideal for someone who thrives in a fast-paced environment and enjoys mentoring others while contributing directly to cutting-edge chip development.
ROLE AND RESPONSIBILITIES
- Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
- Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability
- Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification
- Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.)
- Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing
- Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence
- Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus)
BASIC QUALIFICATIONS
- Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies
- Proven track record of top level integration IP layout macros and preparing IPs for handoff to Physical Design
- Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred)
- At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16)
- Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance
- Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
- Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
- Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools
- Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules
- Experience working in collaborative environments with international and remote teams
- Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams
- Experience using revision control systems for layout design management
PREFERRED QUALIFICATIONS
- Exposure to optical or high-speed analog interfaces is a strong plus
- Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization
- Proven ability to collaborate with international teams (U.S., Canada, Argentina)
- Strong organizational skills with high attention to detail and follow-through
- Ability to multi-task and prioritize in a fast-paced, dynamic environment
- Proactive, eager-to-learn mindset with excellent problem-solving skills
WHAT WE OFFER
- The chance to play a foundational role at a high-growth semiconductor start-up
- Exposure to a wide variety of cross functional teams
- A collaborative, international team culture where ideas and initiative are valued
- The opportunity to grow alongside Celero as we scale and shape the future of our industry
- A foundational role at a fast-growing semiconductor start-up shaping the future of AI and data center connectivity
INTRODUCTION
Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. As we scale rapidly, we are looking for a driven and resourceful High-Speed Analog Layout Engineer to be the backbone of our daily operations and a key partner in shaping our company culture.
We are seeking a Principal/Senior Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits. You will interface closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success. This is a hands-on technical role ideal for someone who thrives in a fast-paced environment and enjoys mentoring others while contributing directly to cutting-edge chip development.
ROLE AND RESPONSIBILITIES
- Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
- Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability
- Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification
- Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.)
- Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing
- Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence
- Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus)
BASIC QUALIFICATIONS
- Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies
- Proven track record of top level integration IP layout macros and preparing IPs for handoff to Physical Design
- Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred)
- At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16)
- Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance
- Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
- Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
- Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools
- Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules
- Experience working in collaborative environments with international and remote teams
- Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams
- Experience using revision control systems for layout design management
PREFERRED QUALIFICATIONS
- Exposure to optical or high-speed analog interfaces is a strong plus
- Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization
- Proven ability to collaborate with international teams (U.S., Canada, Argentina)
- Strong organizational skills with high attention to detail and follow-through
- Ability to multi-task and prioritize in a fast-paced, dynamic environment
- Proactive, eager-to-learn mindset with excellent problem-solving skills
WHAT WE OFFER
- The chance to play a foundational role at a high-growth semiconductor start-up
- Exposure to a wide variety of cross functional teams
- A collaborative, international team culture where ideas and initiative are valued
- The opportunity to grow alongside Celero as we scale and shape the future of our industry
- A foundational role at a fast-growing semiconductor start-up shaping the future of AI and data center connectivity
Layout Design Engineer Jobs by Experience Level
See All 44 Layout Design Engineer Jobs
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Find Layout Design Engineer JobsLayout Design Engineer Job Market
Who's Hiring
Top Industries Hiring
- Electronics & Hardware
- Technology & Software
What Employers Look For
The qualifications that appear most often in layout design engineer jobs.
- Proficiency in Cadence Virtuoso or equivalent EDA layout tools
- Experience with DRC, LVS, and parasitic extraction sign-off flows
- Hands-on work with CMOS process nodes at 28nm or below
- Understanding of analog, RF, or mixed-signal layout techniques
- Bachelor's degree in electrical engineering or a closely related field
- Familiarity with foundry design rule manuals and PDK usage
Tips for Your Layout Design Engineer Job Search
Tailor your resume to EDA tools
List every EDA tool you've used, Cadence Virtuoso, Mentor Calibre, Synopsys ICC2, and the process nodes you've worked in. Hiring managers filter resumes on these specifics before reading anything else.
Show DRC and LVS clean sign-off
Employers care whether your layouts reach tape-out without violations. Call out DRC-clean and LVS-verified designs in your resume's project section, naming the foundry node and technology, so reviewers know you own the full flow.
Apply early to roles that fit
Migrate Mate lists layout design engineer openings from across the United States in one place, so you can find roles that match and apply directly to each listing.
Target postings by process node
Filter openings by the node you know best, 7nm, 28nm, or older CMOS. Roles at advanced nodes are concentrated at foundry-heavy companies, while legacy-node positions appear more broadly in analog and power management teams.
Prepare a layout portfolio with annotations
Bring a PDF of annotated layout screenshots showing your floorplan decisions, shielding strategies, and symmetry techniques. Reviewers who can't share proprietary work still respond well to annotated examples that demonstrate your design reasoning.
Negotiate by citing comparable offers and node complexity
When discussing compensation, reference the seniority of your tape-out experience and the advanced node complexity you've handled. Those two factors drive the widest variation in layout engineer offers, so name them directly in the conversation.
Layout Design Engineer Jobs: Frequently Asked Questions
Which companies are hiring the most layout design engineers?
Apple, NVIDIA, and Celero Communications are hiring the most layout design engineers right now, with openings concentrated in California, Texas, and Wisconsin, based on current listings on Migrate Mate as of November 2026. Demand is especially strong at companies developing custom silicon for AI, automotive, and 5G applications.
How many layout design engineer jobs are remote?
About 60% of layout design engineer openings are fully remote or hybrid as of November 2026, though fully on-site roles remain common because EDA tool licenses and secure IP handling are easier to manage in a lab. Digital backend and verification-adjacent layout roles tend to offer the most remote flexibility compared to analog and RF positions.
How do you become a layout design engineer?
Start with a bachelor's degree in electrical engineering, focusing coursework on VLSI design, semiconductor devices, and circuit theory. Build hands-on experience through academic projects or internships that use EDA tools such as Cadence Virtuoso. Work toward familiarity with DRC and LVS flows, then pursue entry-level roles at fabless companies or foundry design centers where you can run real tape-out projects.
How do you get a layout design engineer job with little experience?
Focus on demonstrating EDA tool proficiency through academic or personal projects, even if the designs are small cells or standard library components. Document every DRC-clean layout you complete and include annotated screenshots in a portfolio. Apply to companies that run intern-to-hire pipelines or entry-level positions tied to mature process nodes, where the design rules are well-documented and onboarding ramps faster.
What does the layout design engineer interview process look like?
Most processes begin with a recruiter screen focused on EDA tools and process node experience, followed by a technical phone interview covering layout concepts like matching, shielding, and latch-up prevention. A take-home or on-site layout exercise is common, where you annotate or complete a small cell to demonstrate your decision-making. Final rounds typically include team fit conversations and a review of your past tape-out contributions with senior engineers.
Where can I find and apply to layout design engineer jobs?
You can find and apply to layout design engineer jobs on Migrate Mate, which lists current openings from across the United States in one place. Search the listings to find roles that match your tool experience, process node background, and seniority level, then apply directly to each listing that fits.
See All 44 Layout Design Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
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