Senior Asic Design Engineer Jobs in California
Senior Asic Design Engineer jobs in California sit at the center of one of the world's most active semiconductor markets, with demand concentrated in consumer electronics, networking infrastructure, data center silicon, and automotive chips across firms ranging from associate to principal level. The heaviest hiring runs through Silicon Valley, San Diego, and the greater Los Angeles area, with established employers like Qualcomm, Intel, and Apple consistently maintaining large ASIC teams in the state. The most sought-after specialties include high-speed SerDes and PHY design, low-power mobile architectures, and custom AI accelerator blocks. Find a role that fits below and apply directly.
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Showing 5 of 89+ Senior Asic Design Engineer jobs
Meet the Team
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Your Impact
- Author design specifications and participate in micro-architecture specification reviews.
- Implement Verilog RTL to meet timing, performance, and power requirements
- Develop and analyze functional coverage.
- Collaborate with the verification team to address design corner cases and close coverage.
- Work closely with physical design team to close design timing and place-and-route issues.
- Perform diagnostic and post silicon validation tests in the lab.
- Bachelor’s degree in Electrical or Computer engineering and 7+ years of ASIC Design related experience, or Master’s degree in Electrical or Computer engineering and 4+ years of ASIC Design related experience, or PhD in Electrical or Computer engineering + 1 year of ASIC Design related experience
- Experience with Verilog/System Verilog
- At least one full ASIC tapeout (advanced nodes preferred).
- Strong RTL skills with good command of timing closure, power, clock gating, and the full ASIC design flow.
- Solid debug and scripting skills.
- Good written and verbal communication skills.
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Message to applicants applying to work in the U.S. and/or Canada:
The starting salary range posted for this position is $167,700.00 to $245,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.
U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:
- 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
- Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
- Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
- 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:
- .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
- 1.5% of incentive target for each 1% of attainment between 50% and 75%;
- 1% of incentive target for each 1% of attainment between 75% and 100%; and
- Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
The applicable full salary ranges for this position, by specific state, are listed below:
New York City Metro Area:
$167,700.00 - $282,000.00
Non-Metro New York state& Washington state:
$149,100.00 - $250,900.00
- For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
Meet the Team
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Your Impact
- Author design specifications and participate in micro-architecture specification reviews.
- Implement Verilog RTL to meet timing, performance, and power requirements
- Develop and analyze functional coverage.
- Collaborate with the verification team to address design corner cases and close coverage.
- Work closely with physical design team to close design timing and place-and-route issues.
- Perform diagnostic and post silicon validation tests in the lab.
- Bachelor’s degree in Electrical or Computer engineering and 7+ years of ASIC Design related experience, or Master’s degree in Electrical or Computer engineering and 4+ years of ASIC Design related experience, or PhD in Electrical or Computer engineering + 1 year of ASIC Design related experience
- Experience with Verilog/System Verilog
- At least one full ASIC tapeout (advanced nodes preferred).
- Strong RTL skills with good command of timing closure, power, clock gating, and the full ASIC design flow.
- Solid debug and scripting skills.
- Good written and verbal communication skills.
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Message to applicants applying to work in the U.S. and/or Canada:
The starting salary range posted for this position is $167,700.00 to $245,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.
U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:
- 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
- Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
- Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
- 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:
- .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
- 1.5% of incentive target for each 1% of attainment between 50% and 75%;
- 1% of incentive target for each 1% of attainment between 75% and 100%; and
- Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
The applicable full salary ranges for this position, by specific state, are listed below:
New York City Metro Area:
$167,700.00 - $282,000.00
Non-Metro New York state& Washington state:
$149,100.00 - $250,900.00
- For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
See All 89 Senior Asic Design Engineer Jobs in California
Find roles in California that match your experience and apply in just a few clicks.
Find JobsSenior Asic Design Engineer Jobs by City in California
Where California roles are concentrated, by current openings.
Senior Asic Design Engineer Job Market in California
A snapshot from current California openings, updated as new roles post.
Who's Hiring
- Google11
- Apple10
- Cisco8
- Qualcomm5
- Amazon5
Top Industries Hiring
- Technology & Software18
- Electronics & Hardware17
- Telecommunications4
- Artificial Intelligence4
- Banking & Financial Services2
What California Employers Look For
The qualifications that appear most often in senior asic design engineer jobs across California.
- Bachelor's or master's degree in electrical engineering or computer engineering required
- Five or more years of RTL design experience in Verilog or SystemVerilog
- Hands-on physical design knowledge including floorplanning, placement, and timing closure
- Experience taping out a full ASIC from RTL to GDSII in a production environment
- Proficiency with industry EDA tools such as Synopsys Design Compiler or Cadence Genus
- Strong understanding of low-power design techniques including clock gating and power gating
Senior Asic Design Engineer Jobs in California: Frequently Asked Questions
How do you become a senior asic design engineer in California?
The most direct path is a bachelor's or master's degree in electrical engineering or computer engineering followed by several years of RTL design experience at a California semiconductor firm. California does not require a state-issued license for ASIC engineering roles, so advancement depends on demonstrated tape-out experience and deep specialization. Many engineers build toward senior level by progressing through associate and mid-level design roles at companies in Silicon Valley or San Diego's large fabless ecosystem.
How much do senior asic design engineers make in California?
Senior asic design engineers in California earn a median of about $185,180 a year, based on May 2025 Bureau of Labor Statistics wage data, ranging from around $126,590 for the lowest 10% to over $281,210 for the top 10%. Pay rises with experience, specialty, and employer.
Which companies hire senior asic design engineers in California?
Employers hiring senior asic design engineers in California right now include Google, Apple, and Cisco, based on current listings on Migrate Mate as of August 2026. California's dense concentration of fabless semiconductor companies and vertically integrated tech firms means hiring is active across a wide range of product areas, from mobile SoCs to data center and automotive chips.
Which California cities have the most senior asic design engineer jobs?
Sunnyvale, San Jose, and Santa Clara have the most senior asic design engineer openings in California. Silicon Valley anchors the bulk of demand through its concentration of fabless chip companies and large tech firms with in-house silicon teams, while San Diego draws heavily from Qualcomm's headquarters and its supplier ecosystem, and Los Angeles reflects growing investment in aerospace and automotive silicon alongside consumer electronics work.
Are there remote senior asic design engineer jobs in California?
Yes, but they're rare. ASIC design involves lab access, EDA tool licenses on secured servers, and close collaboration with physical design and verification teams, which keeps most roles on-site or hybrid. About 31% of senior asic design engineer openings tied to California are remote or hybrid as of August 2026, and the roles most likely to offer flexibility are those focused on RTL coding and microarchitecture definition rather than physical implementation or bring-up.
How can I get hired as a senior asic design engineer in California with little or no experience?
The most realistic entry path is a master's program with a strong digital design thesis followed by an internship or new-grad role at a California fabless company. Firms like Qualcomm, Broadcom, and Marvell run structured new-graduate programs in San Diego and Silicon Valley specifically targeting candidates with academic tape-out or FPGA prototyping experience. Moving from an FPGA design or verification engineering role is a common lateral path, and building a portfolio of RTL projects or contributing to open-source RISC-V cores strengthens a candidate's profile considerably.
Where can I find and apply to senior asic design engineer jobs in California?
You can find and apply to senior asic design engineer jobs in California on Migrate Mate, which lists current California openings from employers actively hiring for this role. Search the available positions, find the roles that fit your experience and location, and apply directly through each listing.
See All 89 Senior Asic Design Engineer Jobs in California
Find roles in California that match your experience and apply in just a few clicks.
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