Senior Asic Design Engineer Jobs in California
Senior Asic Design Engineer jobs in California sit at the center of one of the world's most active semiconductor markets, with demand concentrated in consumer electronics, networking infrastructure, data center silicon, and automotive chips across firms ranging from associate to principal level. The heaviest hiring runs through Silicon Valley, San Diego, and the greater Los Angeles area, with established employers like Qualcomm, Intel, and Apple consistently maintaining large ASIC teams in the state. The most sought-after specialties include high-speed SerDes and PHY design, low-power mobile architectures, and custom AI accelerator blocks. Find a role that fits below and apply directly.
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At Boeing, we innovate and collaborate to make the world a better place. We’re committed to fostering an environment for every teammate that’s welcoming, respectful and inclusive, with great opportunity for professional growth. Find your future with us.
Boeing Defense, Space and Security is hiring ASIC Design Engineers — Design-for-Test (DFT) & Physical Design (Synthesis and Timing) at various levels of experience to join the team in Mountain View, CA.
Boeing Space, Intelligence & Weapons Systems organization is seeking multiple ASIC engineers across experience levels to advance mission‑critical digital subsystems. Candidates may focus on Design‑for‑Test (DFT) / ASIC backend test infrastructure, or on Physical Design (synthesis and static timing analysis) responsibilities. You will work on leading‑edge ASICs used in space and aerospace systems—driving architecture, verification, tapeout readiness, silicon debug, and cross‑discipline integration with architecture, RTL, verification, DFT, and external backend partners.
Position Responsibilities:
- Design and implement DFT architectures and test access mechanisms: TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (BSCAN), MBIST, memory BIST, and scan compression.
- Develop and validate TAP/JTAG and IJTAG infrastructures; produce BSDL/ICL/PDL artifacts; support ATPG pattern generation and coverage optimization.
- Drive pattern generation, memory test validation, at‑speed test, silicon debug (scan, at‑speed, bring‑up), and post‑silicon validation.
- Perform synthesis, equivalence checking, static timing analysis (STA), constraints generation/management, timing convergence and ECO implementation at block and chip level.
- Support clean netlist handoffs and predictable convergence by partnering with RTL, verification, DFT, backend partners, and vendors.
- Support chip‑level integration, top‑level timing closure, signoff readiness, and tapeout activities.
- Contribute to methodology development, automation, tool evaluations, flow documentation, and deployment of best practices for next‑generation products.
- Troubleshoot complex cross‑domain timing and CDC issues; propose and implement robust, repeatable fixes.
- Coordinate with external partners/customers on custom DFT interfaces, security, and backend flows as applicable.
- Mentor engineers and lead technical efforts (for senior/lead levels).
- Occasional travel and after‑hours meetings during critical milestones.
How to make your application stand out: Please include a cover letter or brief summary of relevant DFT or ASIC physical design experience and specific examples of impact (e.g., achieved timing closure on X‑nm blocks, implemented MBIST with Y% coverage, reduced ATPG time by Z%, led ECOs to tapeout).
This position is expected to be 100% onsite. The selected candidate will be required to work onsite at the listed location.
Basic Qualifications (Required Skills/Experience):
- This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required.
- Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
- 5+ years of ASIC/FPGA design for test or physical design experience
- Proficiency in scripting for automation and analysis (Tcl, Python, Perl).
Preferred Qualifications (Desired Skills/Experience):
- Lead, Level 4: 9+ years related engineering experience and demonstrated technical leadership.
- Senior, Level 5: 14+ years related engineering experience and demonstrated technical leadership.
- Strong analytical, problem‑solving, and communication skills
- Bachelor’s or Master’s Degree in EE, Computer Engineering/Science, or related field.
- For DFT roles: Hands‑on expertise with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at‑speed test, and silicon debug. Familiarity with BSDL/ICL/PDL artifacts.
- For Physical Design roles: Practical experience in synthesis and static timing analysis (STA), constraints generation/management, logic synthesis, equivalence checking, and ECO flows.
- Active U.S. Secret Clearance.
- Experience with large, timing‑challenging ASIC blocks, cross‑domain timing convergence, and full physical design flow (synthesis, floorplanning, place & route, CTS, STA, physical verification).
- Background in radiation‑hardened or space‑qualified ASIC design.
- FPGA implementation experience including constraints and timing closure.
- Understanding of timing fundamentals and CDC concepts.
- Familiarity with UPF/CPF power intent, power closure flows, and DFT interplay with power domains.
- Requirements development and traceability experience.
- Experience working with external backend partners, multi‑disciplinary teams, and vendors.
- Familiarity with industry‑standard EDA tools and DFT/physical design methodologies.
- Mentoring, team leadership, or formal technical lead experience.
Conflict of Interest:
Successful candidate for this job must satisfy the Company’s Conflict of Interest (COI) assessment process.
Typical Education/Experience
Experienced, Level 3: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 5 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Lead, Level 4: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 9 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Senior, Level 5: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Relocation:
This position offers relocation based on candidate eligibility. Note: Basic relocation will be offered for eligible internal candidates.
Drug Free Workplace:
Boeing is a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies.
Shift Work:
This position is for 1st shift.
Total Rewards:
At Boeing, we strive to deliver a Total Rewards package that will attract, engage and retain the top talent. Elements of the Total Rewards package include competitive base pay and variable compensation opportunities.
The Boeing Company also provides eligible employees with an opportunity to enroll in a variety of benefit programs, generally including health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs, and a number of programs that provide for both paid and unpaid time away from work.
The specific programs and options available to any given employee may vary depending on eligibility factors such as geographic location, date of hire, and the applicability of collective bargaining agreements.
Pay is based upon candidate experience and qualifications, as well as market and business considerations.
Summary pay range for Experienced, (Level 3): $119,850 - $162,150
Summary pay range for Lead, (Level 4): $146,200 - $197,800
Summary pay range for Senior, (Level 5): $176,800 - $239,200
Applications for this position will be accepted until Oct. 17, 2026
Export Control Requirements:
This position must meet U.S. export control compliance requirements. To meet U.S. export control compliance requirements, a “U.S. Person” as defined by 22 C.F.R. §120.62 is required. “U.S. Person” includes U.S. Citizen, U.S. National, lawful permanent resident, refugee, or asylee.
Export Control Details:
US based job, US Person required
Education
Bachelor's Degree or Equivalent Required
Relocation
This position offers relocation based on candidate eligibility.
Security Clearance
This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret Clearance Post-Start is required.
Visa Sponsorship
Employer will not sponsor applicants for employment visa status.
Shift
This position is for 1st shift
Equal Opportunity Employer:
Boeing is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, physical or mental disability, genetic factors, military/veteran status or other characteristics protected by law.
Your Benefits
No matter where you are in life, our benefits help prepare you for the present and the future.
- Generous company match to your 401(k).
- Industry-leading tuition assistance program pays your institution directly.
- Fertility, adoption, and surrogacy benefits.
- Up to $10,000 gift match when you support your favorite nonprofit organizations.
These programs are subject to eligibility requirements and other conditions, which may differ for employees of certain subsidiaries or business units, or union-represented employees depending on bargaining agreement terms. If this information conflicts with the program documents, the latter shall control. This material is informational only.
At Boeing, we innovate and collaborate to make the world a better place. We’re committed to fostering an environment for every teammate that’s welcoming, respectful and inclusive, with great opportunity for professional growth. Find your future with us.
Boeing Defense, Space and Security is hiring ASIC Design Engineers — Design-for-Test (DFT) & Physical Design (Synthesis and Timing) at various levels of experience to join the team in Mountain View, CA.
Boeing Space, Intelligence & Weapons Systems organization is seeking multiple ASIC engineers across experience levels to advance mission‑critical digital subsystems. Candidates may focus on Design‑for‑Test (DFT) / ASIC backend test infrastructure, or on Physical Design (synthesis and static timing analysis) responsibilities. You will work on leading‑edge ASICs used in space and aerospace systems—driving architecture, verification, tapeout readiness, silicon debug, and cross‑discipline integration with architecture, RTL, verification, DFT, and external backend partners.
Position Responsibilities:
- Design and implement DFT architectures and test access mechanisms: TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (BSCAN), MBIST, memory BIST, and scan compression.
- Develop and validate TAP/JTAG and IJTAG infrastructures; produce BSDL/ICL/PDL artifacts; support ATPG pattern generation and coverage optimization.
- Drive pattern generation, memory test validation, at‑speed test, silicon debug (scan, at‑speed, bring‑up), and post‑silicon validation.
- Perform synthesis, equivalence checking, static timing analysis (STA), constraints generation/management, timing convergence and ECO implementation at block and chip level.
- Support clean netlist handoffs and predictable convergence by partnering with RTL, verification, DFT, backend partners, and vendors.
- Support chip‑level integration, top‑level timing closure, signoff readiness, and tapeout activities.
- Contribute to methodology development, automation, tool evaluations, flow documentation, and deployment of best practices for next‑generation products.
- Troubleshoot complex cross‑domain timing and CDC issues; propose and implement robust, repeatable fixes.
- Coordinate with external partners/customers on custom DFT interfaces, security, and backend flows as applicable.
- Mentor engineers and lead technical efforts (for senior/lead levels).
- Occasional travel and after‑hours meetings during critical milestones.
How to make your application stand out: Please include a cover letter or brief summary of relevant DFT or ASIC physical design experience and specific examples of impact (e.g., achieved timing closure on X‑nm blocks, implemented MBIST with Y% coverage, reduced ATPG time by Z%, led ECOs to tapeout).
This position is expected to be 100% onsite. The selected candidate will be required to work onsite at the listed location.
Basic Qualifications (Required Skills/Experience):
- This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required.
- Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
- 5+ years of ASIC/FPGA design for test or physical design experience
- Proficiency in scripting for automation and analysis (Tcl, Python, Perl).
Preferred Qualifications (Desired Skills/Experience):
- Lead, Level 4: 9+ years related engineering experience and demonstrated technical leadership.
- Senior, Level 5: 14+ years related engineering experience and demonstrated technical leadership.
- Strong analytical, problem‑solving, and communication skills
- Bachelor’s or Master’s Degree in EE, Computer Engineering/Science, or related field.
- For DFT roles: Hands‑on expertise with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at‑speed test, and silicon debug. Familiarity with BSDL/ICL/PDL artifacts.
- For Physical Design roles: Practical experience in synthesis and static timing analysis (STA), constraints generation/management, logic synthesis, equivalence checking, and ECO flows.
- Active U.S. Secret Clearance.
- Experience with large, timing‑challenging ASIC blocks, cross‑domain timing convergence, and full physical design flow (synthesis, floorplanning, place & route, CTS, STA, physical verification).
- Background in radiation‑hardened or space‑qualified ASIC design.
- FPGA implementation experience including constraints and timing closure.
- Understanding of timing fundamentals and CDC concepts.
- Familiarity with UPF/CPF power intent, power closure flows, and DFT interplay with power domains.
- Requirements development and traceability experience.
- Experience working with external backend partners, multi‑disciplinary teams, and vendors.
- Familiarity with industry‑standard EDA tools and DFT/physical design methodologies.
- Mentoring, team leadership, or formal technical lead experience.
Conflict of Interest:
Successful candidate for this job must satisfy the Company’s Conflict of Interest (COI) assessment process.
Typical Education/Experience
Experienced, Level 3: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 5 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Lead, Level 4: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 9 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Senior, Level 5: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Relocation:
This position offers relocation based on candidate eligibility. Note: Basic relocation will be offered for eligible internal candidates.
Drug Free Workplace:
Boeing is a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies.
Shift Work:
This position is for 1st shift.
Total Rewards:
At Boeing, we strive to deliver a Total Rewards package that will attract, engage and retain the top talent. Elements of the Total Rewards package include competitive base pay and variable compensation opportunities.
The Boeing Company also provides eligible employees with an opportunity to enroll in a variety of benefit programs, generally including health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs, and a number of programs that provide for both paid and unpaid time away from work.
The specific programs and options available to any given employee may vary depending on eligibility factors such as geographic location, date of hire, and the applicability of collective bargaining agreements.
Pay is based upon candidate experience and qualifications, as well as market and business considerations.
Summary pay range for Experienced, (Level 3): $119,850 - $162,150
Summary pay range for Lead, (Level 4): $146,200 - $197,800
Summary pay range for Senior, (Level 5): $176,800 - $239,200
Applications for this position will be accepted until Oct. 17, 2026
Export Control Requirements:
This position must meet U.S. export control compliance requirements. To meet U.S. export control compliance requirements, a “U.S. Person” as defined by 22 C.F.R. §120.62 is required. “U.S. Person” includes U.S. Citizen, U.S. National, lawful permanent resident, refugee, or asylee.
Export Control Details:
US based job, US Person required
Education
Bachelor's Degree or Equivalent Required
Relocation
This position offers relocation based on candidate eligibility.
Security Clearance
This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret Clearance Post-Start is required.
Visa Sponsorship
Employer will not sponsor applicants for employment visa status.
Shift
This position is for 1st shift
Equal Opportunity Employer:
Boeing is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, physical or mental disability, genetic factors, military/veteran status or other characteristics protected by law.
Your Benefits
No matter where you are in life, our benefits help prepare you for the present and the future.
- Generous company match to your 401(k).
- Industry-leading tuition assistance program pays your institution directly.
- Fertility, adoption, and surrogacy benefits.
- Up to $10,000 gift match when you support your favorite nonprofit organizations.
These programs are subject to eligibility requirements and other conditions, which may differ for employees of certain subsidiaries or business units, or union-represented employees depending on bargaining agreement terms. If this information conflicts with the program documents, the latter shall control. This material is informational only.
See All 93 Senior Asic Design Engineer Jobs in California
Find roles in California that match your experience and apply in just a few clicks.
Find JobsSenior Asic Design Engineer Jobs by City in California
Where California roles are concentrated, by current openings.
Senior Asic Design Engineer Job Market in California
A snapshot from current California openings, updated as new roles post.
Who's Hiring
- Google11
- Qualcomm10
- Apple8
- Cisco6
- NVIDIA5
Top Industries Hiring
- Technology & Software
- Electronics & Hardware
- Telecommunications
- Law & Legal Services
- Media & Entertainment
What California Employers Look For
The qualifications that appear most often in senior asic design engineer jobs across California.
- Bachelor's or master's degree in electrical engineering or computer engineering required
- Five or more years of RTL design experience in Verilog or SystemVerilog
- Hands-on physical design knowledge including floorplanning, placement, and timing closure
- Experience taping out a full ASIC from RTL to GDSII in a production environment
- Proficiency with industry EDA tools such as Synopsys Design Compiler or Cadence Genus
- Strong understanding of low-power design techniques including clock gating and power gating
Senior Asic Design Engineer Jobs in California: Frequently Asked Questions
How do you become a senior asic design engineer in California?
The most direct path is a bachelor's or master's degree in electrical engineering or computer engineering followed by several years of RTL design experience at a California semiconductor firm. California does not require a state-issued license for ASIC engineering roles, so advancement depends on demonstrated tape-out experience and deep specialization. Many engineers build toward senior level by progressing through associate and mid-level design roles at companies in Silicon Valley or San Diego's large fabless ecosystem.
How much do senior asic design engineers make in California?
Senior asic design engineers in California earn a median of about $185,180 a year, based on May 2025 Bureau of Labor Statistics wage data, ranging from around $126,590 for the lowest 10% to over $281,210 for the top 10%. Pay rises with experience, specialty, and employer.
Which companies hire senior asic design engineers in California?
Employers hiring senior asic design engineers in California right now include Google, Qualcomm, and Apple, based on current listings on Migrate Mate as of October 2026. California's dense concentration of fabless semiconductor companies and vertically integrated tech firms means hiring is active across a wide range of product areas, from mobile SoCs to data center and automotive chips.
Which California cities have the most senior asic design engineer jobs?
Sunnyvale, Santa Clara, and San Jose have the most senior asic design engineer openings in California. Silicon Valley anchors the bulk of demand through its concentration of fabless chip companies and large tech firms with in-house silicon teams, while San Diego draws heavily from Qualcomm's headquarters and its supplier ecosystem, and Los Angeles reflects growing investment in aerospace and automotive silicon alongside consumer electronics work.
Are there remote senior asic design engineer jobs in California?
Yes, but they're rare. ASIC design involves lab access, EDA tool licenses on secured servers, and close collaboration with physical design and verification teams, which keeps most roles on-site or hybrid. About 39% of senior asic design engineer openings tied to California are remote or hybrid as of October 2026, and the roles most likely to offer flexibility are those focused on RTL coding and microarchitecture definition rather than physical implementation or bring-up.
How can I get hired as a senior asic design engineer in California with little or no experience?
The most realistic entry path is a master's program with a strong digital design thesis followed by an internship or new-grad role at a California fabless company. Firms like Qualcomm, Broadcom, and Marvell run structured new-graduate programs in San Diego and Silicon Valley specifically targeting candidates with academic tape-out or FPGA prototyping experience. Moving from an FPGA design or verification engineering role is a common lateral path, and building a portfolio of RTL projects or contributing to open-source RISC-V cores strengthens a candidate's profile considerably.
Where can I find and apply to senior asic design engineer jobs in California?
You can find and apply to senior asic design engineer jobs in California on Migrate Mate, which lists current California openings from employers actively hiring for this role. Search the available positions, find the roles that fit your experience and location, and apply directly through each listing.
See All 93 Senior Asic Design Engineer Jobs in California
Find roles in California that match your experience and apply in just a few clicks.
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