Senior Asic Design Engineer Jobs
Senior Asic Design Engineer jobs are open across semiconductor, consumer electronics, aerospace, and defense industries, from mid-level to principal and staff engineer, with specializations in RTL design, physical design, and verification. Find a role that fits from the openings below and apply directly.
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Job Description:
Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products. This Floorplan Engineer role focuses on chip-level physical architecture and integration for advanced ASICs operating at speeds exceeding 1 GHz, from concept through production. The position provides hands-on experience with the latest 3 nm and smaller process nodes, defining and optimizing the overall die layout, including partitioning, hierarchy, and placement of major functional blocks, memories, and I/O structures for AI, computing, and networking SoCs.
Key Responsibilities
- Define and optimize top-level floorplan architecture, including die size estimation, hierarchy definition, and partitioning.
- Drive macro placement, power grid design, clock distribution planning, pin placement, and feedthrough optimization.
- Collaborate closely with RTL, timing, and packaging teams to balance performance, power, and area (PPA) targets.
- Lead top-level timing closure, congestion analysis, and ECO implementation to ensure clean tapeout readiness.
- Coordinate with block owners and integration teams for smooth block-level to top-level convergence.
- Support cross-functional design integration, providing guidance and technical support to internal and external partners.
- Apply a deep understanding of block PnR, timing closure, physical verification, and IR/EM analysis to achieve signoff-quality results.
- Contribute to design flow automation and methodology development for advanced process technologies.
Technical Skills / Background
- Strong foundation in VLSI design principles and ASIC physical design fundamentals.
- In-depth experience with floorplanning, die partitioning, and hierarchical design.
- Working knowledge of PLLs, clock networks, power delivery, and timing-critical structures.
- Proven ability to drive PPA optimization through innovative layout and planning strategies.
Coding & Tool Proficiency
- Strong experience with TCL scripting and Linux environments is required.
- Proficiency in Python, Perl, or Ruby is preferred.
- Experience with Cadence or equivalent physical design tools is highly desirable.
Collaboration and Leadership
- Excellent communication, organizational, and problem-solving skills.
- Ability to work effectively with customers and cross-functional teams across global sites and time zones.
- Skilled at organizing and presenting large data sets, managing multiple priorities efficiently.
- Exercises independent judgment and strong engineering insight in defining methods, techniques, and evaluation criteria.
- Provides technical leadership, mentors others, and leads execution of new initiatives.
Education and Experience
- BS in Electrical or Computer Engineering with 12+ years of relevant experience, or
- MS in Electrical or Computer Engineering with 10+ years of relevant experience.
Compensation and Benefits
The annual base salary range for this position is USD To USD
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Please Note:
1. If you are a first time user, please create your candidate login account before you apply for a job.
2. If you already have a Candidate Account, please Sign-In before you apply.
Job Description:
Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products. This Floorplan Engineer role focuses on chip-level physical architecture and integration for advanced ASICs operating at speeds exceeding 1 GHz, from concept through production. The position provides hands-on experience with the latest 3 nm and smaller process nodes, defining and optimizing the overall die layout, including partitioning, hierarchy, and placement of major functional blocks, memories, and I/O structures for AI, computing, and networking SoCs.
Key Responsibilities
- Define and optimize top-level floorplan architecture, including die size estimation, hierarchy definition, and partitioning.
- Drive macro placement, power grid design, clock distribution planning, pin placement, and feedthrough optimization.
- Collaborate closely with RTL, timing, and packaging teams to balance performance, power, and area (PPA) targets.
- Lead top-level timing closure, congestion analysis, and ECO implementation to ensure clean tapeout readiness.
- Coordinate with block owners and integration teams for smooth block-level to top-level convergence.
- Support cross-functional design integration, providing guidance and technical support to internal and external partners.
- Apply a deep understanding of block PnR, timing closure, physical verification, and IR/EM analysis to achieve signoff-quality results.
- Contribute to design flow automation and methodology development for advanced process technologies.
Technical Skills / Background
- Strong foundation in VLSI design principles and ASIC physical design fundamentals.
- In-depth experience with floorplanning, die partitioning, and hierarchical design.
- Working knowledge of PLLs, clock networks, power delivery, and timing-critical structures.
- Proven ability to drive PPA optimization through innovative layout and planning strategies.
Coding & Tool Proficiency
- Strong experience with TCL scripting and Linux environments is required.
- Proficiency in Python, Perl, or Ruby is preferred.
- Experience with Cadence or equivalent physical design tools is highly desirable.
Collaboration and Leadership
- Excellent communication, organizational, and problem-solving skills.
- Ability to work effectively with customers and cross-functional teams across global sites and time zones.
- Skilled at organizing and presenting large data sets, managing multiple priorities efficiently.
- Exercises independent judgment and strong engineering insight in defining methods, techniques, and evaluation criteria.
- Provides technical leadership, mentors others, and leads execution of new initiatives.
Education and Experience
- BS in Electrical or Computer Engineering with 12+ years of relevant experience, or
- MS in Electrical or Computer Engineering with 10+ years of relevant experience.
Compensation and Benefits
The annual base salary range for this position is USD To USD
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Senior Asic Design Engineer Jobs by Experience Level
Top Cities Hiring Senior Asic Design Engineers
Explore senior asic design engineer openings in the cities hiring most right now.
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Find JobsSenior Asic Design Engineer Job Market
Who's Hiring
- Lockheed Martin19
- Cisco12
- Qualcomm11
- Hewlett Packard Enterprise | HPE11
- K2 Space10
Top Industries Hiring
- Technology & Software12
- Electronics & Hardware7
- Telecommunications3
- Media & Entertainment1
- Artificial Intelligence1
What Employers Look For
The qualifications that appear most often in senior asic design engineer jobs.
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
- Proficiency in RTL design using Verilog or SystemVerilog
- Experience with industry-standard EDA tools such as Synopsys or Cadence
- Hands-on experience with full ASIC design flow from specification through tapeout
- Familiarity with timing closure, DFT, and low-power design techniques
- Strong understanding of physical design constraints and semiconductor process nodes
Tips for Your Senior Asic Design Engineer Job Search
Tailor your resume for each design stage
Recruiters scanning senior asic design engineer resumes look for which phases you own: RTL, synthesis, place-and-route, or signoff. List each stage explicitly rather than grouping them under a generic 'design experience' bullet so your depth is immediately clear.
Highlight tapeout experience with specifics
Tapeout credits are a strong differentiator at the senior level. Name the process nodes you've worked on and whether you led or contributed to each tapeout. Employers use this to gauge both technical depth and your ability to deliver under production deadlines.
Apply early to roles that fit
Migrate Mate lists senior asic design engineer openings from across the United States in one place, so you can find roles that match and apply directly to each listing.
Filter openings by process node requirement
Many senior asic design engineer postings specify a preferred node, such as 7nm, 5nm, or 3nm. Applying to roles that match your node experience avoids early screening cuts and signals you can contribute from day one without a long ramp-up.
Prepare a design walkthrough for interviews
Senior-level ASIC interviews almost always include a deep-dive on a past design. Be ready to walk through architecture choices, timing closure decisions, and tradeoffs you made. Generic process answers without concrete design context rarely pass the technical bar at this level.
Negotiate beyond base salary at offer stage
Total compensation for senior asic design engineers typically includes equity, sign-on bonuses, and tape-out bonuses. Before accepting, ask specifically about each component and vesting schedules so you can compare offers on equivalent terms rather than base alone.
Senior Asic Design Engineer Jobs: Frequently Asked Questions
Which companies are hiring the most senior asic design engineers?
The companies hiring the most senior asic design engineers right now include Lockheed Martin, Cisco, and Qualcomm, with the largest share of openings in California, Texas, and Colorado, based on current listings on Migrate Mate as of November 2026. Semiconductor companies and hyperscalers building custom silicon consistently account for the highest volume of senior-level postings.
How many senior asic design engineer jobs are remote?
About 46% of senior asic design engineer openings are fully remote or hybrid as of November 2026, which is lower than many engineering disciplines because tapeout cycles often require on-site lab access. Roles focused on RTL design and functional verification tend to offer the most remote flexibility, while physical design and silicon bring-up positions are more likely to require on-site presence.
How do you become a senior asic design engineer?
You typically start with a degree in electrical or computer engineering, then build hands-on RTL design skills through junior roles or graduate research. Gaining end-to-end tapeout experience across multiple projects is the key milestone that moves engineers from mid-level to senior. Deepening expertise in a specific domain like low-power design, high-speed interfaces, or verification accelerates that transition. Familiarity with EDA tools used in production flows is expected before most senior interviews.
Can I get hired as a senior asic design engineer without direct ASIC experience?
Moving into a senior asic design engineer role from an adjacent background is difficult but possible if you can demonstrate transferable depth. Engineers coming from FPGA design, digital signal processing, or custom analog design have successfully transitioned by completing relevant coursework, contributing to open-source RTL projects, or pursuing contract tapeout work to build a portfolio. Employers expect you to close the gap before applying rather than planning to learn on the job.
What does the senior asic design engineer interview process look like?
The process typically begins with a recruiter screen focused on your design background and tool experience, followed by a technical phone screen covering RTL concepts and timing fundamentals. On-site or virtual loops usually include a design exercise, a deep-dive walkthrough of a past project, and system-level architecture questions. Some companies add a coding round focused on hardware description languages or scripting. Final rounds often involve a hiring manager conversation about project ownership and cross-functional collaboration.
Where can I find and apply to senior asic design engineer jobs?
You can find and apply to senior asic design engineer jobs on Migrate Mate, which lists current openings from across the United States. Find the roles that match your experience and apply directly to each listing from the page.
See All 177+ Senior Asic Design Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
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