Senior Asic Design Engineer Jobs in Sunnyvale, CA
Senior Asic Design Engineer jobs in Sunnyvale are concentrated in the city's semiconductor and fabless chip corridors, particularly around the Lawrence Expressway corridor, Moffett Park, and downtown Sunnyvale, where employers across consumer electronics, wireless communications, and AI hardware are actively hiring. Google, Apple, and Meta are among the companies with open roles. See the openings below and apply to the ones that match your experience.
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Showing 5 of 98+ Senior Asic Design Engineer jobs
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Sunnyvale, CA, USA; Tel Aviv, Israel; Haifa, Israel.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 8 years of experience in design verification (DV) with a focus on digital signal processing (DSP), communication systems, or arithmetic logic blocks.
- Experience with scripting in Python, Perl, or Makefile for automation.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
- Experience with Mixed-Signal verification techniques such as Real Number Modeling (RNM, SystemVerilog-Wreal) or SystemVerilog-AMS.
- Functional knowledge of adaptive equalization architectures (FFE/DFE) and timing recovery loops.
- Programming proficiency in Python, MATLAB, or C/C++ for testbench automation and reference modeling.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will define and execute the verification strategy for high-speed Physical Layer (PHY) digital blocks. This role focuses on the functional and mathematical verification of complex DSP algorithms, digital-analog boundaries, and signal processing logic. This position requires a strong technical foundation in communication theory, fixed-point arithmetic, and mixed-signal co-simulation.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Verify RTL implementations against high-level architectural reference models (MATLAB, C++, or SystemC) using bit-exact and fixed-point verification methodologies.
- Verify the stability, tracking capability, and convergence of adaptive equalization loops (FFE, DFE) and timing recovery systems under varying channel impairments.
- Model and verify the functional interface between Digital DSP blocks and the Analog Front End (AFE) using Real Number Modeling (RNM) or SystemVerilog-AMS.
- Design, implement, and maintain scalable UVM-based simulation environments, SystemVerilog Assertions (SVA), and functional coverage metrics for digital signal processing blocks.
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Sunnyvale, CA, USA; Tel Aviv, Israel; Haifa, Israel.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 8 years of experience in design verification (DV) with a focus on digital signal processing (DSP), communication systems, or arithmetic logic blocks.
- Experience with scripting in Python, Perl, or Makefile for automation.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
- Experience with Mixed-Signal verification techniques such as Real Number Modeling (RNM, SystemVerilog-Wreal) or SystemVerilog-AMS.
- Functional knowledge of adaptive equalization architectures (FFE/DFE) and timing recovery loops.
- Programming proficiency in Python, MATLAB, or C/C++ for testbench automation and reference modeling.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will define and execute the verification strategy for high-speed Physical Layer (PHY) digital blocks. This role focuses on the functional and mathematical verification of complex DSP algorithms, digital-analog boundaries, and signal processing logic. This position requires a strong technical foundation in communication theory, fixed-point arithmetic, and mixed-signal co-simulation.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Verify RTL implementations against high-level architectural reference models (MATLAB, C++, or SystemC) using bit-exact and fixed-point verification methodologies.
- Verify the stability, tracking capability, and convergence of adaptive equalization loops (FFE, DFE) and timing recovery systems under varying channel impairments.
- Model and verify the functional interface between Digital DSP blocks and the Analog Front End (AFE) using Real Number Modeling (RNM) or SystemVerilog-AMS.
- Design, implement, and maintain scalable UVM-based simulation environments, SystemVerilog Assertions (SVA), and functional coverage metrics for digital signal processing blocks.
See All 98 Senior Asic Design Engineer Jobs in Sunnyvale
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Find JobsSenior Asic Design Engineer Job Market in Sunnyvale
Who's Hiring
- Google30
- Apple20
- Meta17
- Synopsys7
- Tensordyne7
Top Industries Hiring
- Technology & Software14
- Artificial Intelligence7
- Banking & Financial Services7
- Electronics & Hardware3
- Construction & Real Estate3
Senior Asic Design Engineer Jobs in Sunnyvale: Frequently Asked Questions
How do I get a senior asic design engineer job in Sunnyvale?
Sunnyvale's semiconductor and consumer electronics clusters are the primary hiring ground, so targeting fabless chip companies and hardware-focused divisions of larger tech firms gives you the most options. Deep expertise in RTL design, physical design closure, or analog mixed-signal work is what local employers look for first. Building connections through Sunnyvale and Silicon Valley IEEE events, and having tape-out experience on your resume, gives you a measurable edge in this market.
Which companies hire senior asic design engineers in Sunnyvale?
Employers hiring senior asic design engineers in Sunnyvale right now include Google, Apple, and Meta, based on current listings on Migrate Mate as of September 2026. Sunnyvale attracts both established semiconductor firms and well-funded fabless startups, making it one of the densest markets for this role in the country.
Are there remote senior asic design engineer jobs in Sunnyvale?
Remote opportunities are limited for senior asic design engineers because hands-on lab access, chip bring-up, and close collaboration with physical design and verification teams typically require on-site presence. About 29% of senior asic design engineer openings tied to Sunnyvale are remote or hybrid as of September 2026, with the remote portion skewed toward pre-silicon architecture and front-end RTL roles rather than back-end physical implementation.
How can I get a senior asic design engineer job in Sunnyvale with little or no experience?
The most realistic entry path in Sunnyvale is through a junior or associate ASIC design role at a mid-size fabless company, where smaller teams give early-career engineers broader tape-out exposure faster than large corporations. Sunnyvale startups in the AI chip and wireless sectors often hire new graduates from strong VLSI programs and value hands-on project work, internships, and any tapeout contributions from academic or open-source chip projects over pedigree alone.
Which industries hire the most senior asic design engineers in Sunnyvale?
Sunnyvale senior asic design engineer roles concentrate in Technology & Software, Artificial Intelligence, and Banking & Financial Services, based on current listings on Migrate Mate as of September 2026. Sunnyvale's long history as a semiconductor hub, anchored by decades of chip company presence and a dense ecosystem of EDA tool vendors and IP providers, continues to make those sectors the dominant source of local demand.
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