Senior Asic Design Engineer Jobs in Sunnyvale, CA
Senior Asic Design Engineer jobs in Sunnyvale are concentrated in the city's semiconductor and fabless chip corridors, particularly around the Lawrence Expressway corridor, Moffett Park, and downtown Sunnyvale, where employers across consumer electronics, wireless communications, and AI hardware are actively hiring. Google, Meta, and Tensordyne are among the companies with open roles. See the openings below and apply to the ones that match your experience.
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Fortinet is looking for a passionate ASIC Designer to join our R&D team! As a key member of Fortinet’s ASIC design group, you will help architect and design our next-generation FortiASIC technology to accelerate the world’s most powerful network security systems.
This role involves working on cutting-edge, high-performance ASIC design from initial specification through RTL implementation. You will play a leading role in developing next-generation AI powered network processing ASIC architecture, performing IP integration, and delivering chip-level RTL design and verification. The ideal candidate is self-motivated, thrives in fast-paced environments with challenging schedules, and possesses a strong technical foundation across all phases of the ASIC design lifecycle—including RTL design, chip-level verification, coverage analysis, and Static Timing Analysis (STA). Deep knowledge of computer networking, machine learning, LLM acceleration, and ASIC design methodologies is essential.
Job Responsibilities
- Micro-Architecture: Collaborate with the architecture team to define and refine the micro-architecture of next-generation FortiASICs.
- Verification & Coverage: Partner with Design Verification (DV) teams to review test plans, perform coverage analysis, and execute full-chip simulations.
- RTL & Design Implementation: Implement designs using SystemVerilog/Verilog HDL, conduct Lint/CDC reviews, perform logic synthesis, execute timing analysis, and manage IP integration.
- Physical Design & PPA: Work with physical design teams to verify constraints, optimize placement and routing, close timing, and achieve optimal Power, Performance, and Area (PPA).
- FPGA Prototyping: Emulate and prototype designs using FPGAs to execute complete debug and validation cycles.
- Bring-Up & Support: Participate in system/board-level bring-up, post-silicon debugging, and ongoing technical support.
- Execution & Collaboration: Act as a self-starter who manages time effectively while collaborating with a diverse, cross-functional engineering team.
Qualifications & Experience
- 8+ years of experience in high-performance networking or processor design.
- Proven track record of taking complex ASIC/FPGA designs from initial concept to mass production.
- Hands-on expertise in Verilog / SystemVerilog HDL coding, synthesis, and design verification.
- In-depth experience across the entire high-performance ASIC development lifecycle—from specification drafting through system bring-up.
- Strong understanding of SystemVerilog and UVM verification methodologies.
- Strong background in AI/LLM accelerator or NPU (Neural Processing Unit) design.
- Strong problem-solving skills, attention to detail, and a collaborative mindset with strong written and verbal communication skills.
Preferred Qualifications:
- Experience with Altera (Intel) / AMD Xilinx FPGA architectures, EDA tools, and IP portfolios.
- Deep understanding of Ethernet protocols and the TCP/IP networking stack .
- Experience in microprocessor architecture, programmable logic design, or custom domain-specific accelerators.
Educational Requirements
- B.S. or M.S. in Electrical Engineering (EE), Computer Engineering (CE), Computer Science (CS), or a related technical field.
Must be authorized to work in the U.S. without sponsorship.
The US base salary range for this full-time position is $192,000-$235,000. Fortinet offers employees a variety of benefits, including medical, dental, vision, life and disability insurance, 401(k), 11 paid holidays, vacation time, and sick time, as well as a comprehensive leave program.
Wage ranges are based on various factors, including the labour market, job type, and job level. Exact salary offers will be determined by factors such as the candidate's subject knowledge, skill level, qualifications, experience, and geographic location.
All roles are eligible to participate in the Fortinet equity program. Bonus eligibility is reviewed at the time of hire and annually at the Company’s discretion.
Why Join Us:
We encourage candidates from all backgrounds and identities to apply. We offer a supportive work environment and a competitive Total Rewards package to support you with your overall health and financial well-being.
Embark on a challenging, enjoyable, and rewarding career journey with Fortinet. Join us in bringing solutions that make a meaningful and lasting impact to our 890,000+ customers around the globe.
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Find JobsSenior Asic Design Engineer Job Market in Sunnyvale
Who's Hiring
- Google25

- Meta17

- Tensordyne13

- Amazon8

- Hewlett Packard Enterprise | HPE8

Top Industries Hiring
- Technology & Software
- Artificial Intelligence
Senior Asic Design Engineer Jobs in Sunnyvale: Frequently Asked Questions
How do I get a senior asic design engineer job in Sunnyvale?
Sunnyvale's semiconductor and consumer electronics clusters are the primary hiring ground, so targeting fabless chip companies and hardware-focused divisions of larger tech firms gives you the most options. Deep expertise in RTL design, physical design closure, or analog mixed-signal work is what local employers look for first. Building connections through Sunnyvale and Silicon Valley IEEE events, and having tape-out experience on your resume, gives you a measurable edge in this market.
Which companies hire senior asic design engineers in Sunnyvale?
Employers hiring senior asic design engineers in Sunnyvale right now include Google, Meta, and Tensordyne, based on current listings on Migrate Mate as of November 2026. Sunnyvale attracts both established semiconductor firms and well-funded fabless startups, making it one of the densest markets for this role in the country.
Are there remote senior asic design engineer jobs in Sunnyvale?
Remote opportunities are limited for senior asic design engineers because hands-on lab access, chip bring-up, and close collaboration with physical design and verification teams typically require on-site presence. About 68% of senior asic design engineer openings tied to Sunnyvale are remote or hybrid as of November 2026, with the remote portion skewed toward pre-silicon architecture and front-end RTL roles rather than back-end physical implementation.
How can I get a senior asic design engineer job in Sunnyvale with little or no experience?
The most realistic entry path in Sunnyvale is through a junior or associate ASIC design role at a mid-size fabless company, where smaller teams give early-career engineers broader tape-out exposure faster than large corporations. Sunnyvale startups in the AI chip and wireless sectors often hire new graduates from strong VLSI programs and value hands-on project work, internships, and any tapeout contributions from academic or open-source chip projects over pedigree alone.
Which industries hire the most senior asic design engineers in Sunnyvale?
Sunnyvale senior asic design engineer roles concentrate in Technology & Software and Artificial Intelligence, based on current listings on Migrate Mate as of November 2026. Sunnyvale's long history as a semiconductor hub, anchored by decades of chip company presence and a dense ecosystem of EDA tool vendors and IP providers, continues to make those sectors the dominant source of local demand.
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