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JOB DETAILS:

JOB DESCRIPTION:

As a Physical Design Timing Engineer, you will play a pivotal role in shaping the performance and efficiency of cutting-edge DDRPHY IP design. Your expertise in timing analysis, optimization, and clock network design will directly contribute to delivering high-performance, low-power solutions that drive Intel's innovative products forward. Working at the intersection of architecture, logic design, and physical design, you will have the unique opportunity to influence methodologies, ensure design robustness, and optimize power and performance, making a meaningful impact on Intel's industry-leading technologies.

Key Responsibilities:

• Perform chip/block-level timing analysis and optimization for IP, identifying and resolving violations to ensure functionality and performance targets are met.
• Generate and verify timing constraints, conducting timing rollups for efficient physical design processes.
• Design and optimize power and performance-efficient clock networks, ensuring adherence to product requirements.
• Develop and refine methodologies for high-quality timing models to streamline physical design workflows.
• Define process, voltage, and temperature (PVT) conditions for timing analysis based on operating conditions and product binning plans.
• Collaborate with architecture, clock design, and logic design teams to develop integration workflows and validate clock network guidelines.
• Work closely with backend design teams for clock balance, timing corrections, power delivery, and partitioning strategies.
• Conduct noise glitch and signal integrity analysis, ensuring design robustness under diverse conditions.
• Contribute to tools, flows, and methodology (TFM) development to support efficient implementation and optimization processes.

QUALIFICATIONS

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications:

• Bachelor's degree with 6+ years of experience, or Master's degree with 4+ years of experience, or PhD with 2+ years of experience in Electrical Engineering, Computer Engineering, or a related field in physical design timing engineering or SoC development.

2+ years of experience with the following skills:

• Proficiency in static timing analysis tools and methodologies.
• Expertise in clock design, timing budgeting, and constraint adaptation.
• Hands-on experience with TCL scripting for flow development and optimization.
• Strong technical knowledge of physical design fundamentals, including extraction, noise glitch analysis, and signal integrity.
• Familiarity with FEM/PV scaling methods and library characterization.

Preferred Qualifications:

• Previous experience in memory design, collaborating across architecture, design, and physical implementation teams.
• Demonstrated problem-solving skills and ability to address complex timing challenges under tight deadlines.
• Effective communication and teamwork abilities to contribute in a cross-functional environment.
• Experience in developing tools, methodologies, or workflows that enhance physical design efficiency.

We invite you to be part of Intel's journey to deliver transformative technologies. Apply today to contribute to pioneering advancements in semiconductor design and innovation.

JOB TYPE:

Experienced Hire

SHIFT:

Shift 1 (United States of America)

PRIMARY LOCATION:

US, Arizona, Phoenix

ADDITIONAL LOCATIONS:

US, California, Folsom
US, California, Santa Clara
US, Oregon, Hillsboro

BUSINESS GROUP:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

POSTING STATEMENT:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

POSITION OF TRUST

N/A

BENEFITS

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

WORK MODEL FOR THIS ROLE

This role will require an on-site presence. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.