Senior Asic Design Engineer Jobs in USA with Visa Sponsorship
Senior ASIC Design Engineer roles attract strong H-1B visa and O-1 visa sponsorship from semiconductor and defense companies. Employers filing LCAs for this specialty occupation regularly sponsor experienced engineers with RTL, synthesis, and timing closure expertise. For detailed occupation requirements, see the O*NET profile.
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About this opportunity:
Design Verification Engineer
ASIC, SoC & FPGA Verification | Ericsson Silicon | Austin, Texas
Build the Verification Foundation for Next-Generation Silicon.
Ericsson Silicon is looking for a results-driven Design Verification Engineer to help develop and validate the ASICs, SoCs, and FPGA-based platforms powering next-generation communications infrastructure.
In this role, you will contribute to verification activities across the product lifecycle—from testbench architecture and constrained-random verification through coverage closure, regression automation, gate-level validation, and post-silicon correlation. You will work closely with architects, RTL designers, emulation teams, and system engineers to identify issues early, accelerate tapeout, and deliver high-quality silicon.
This is an opportunity to make a direct impact on complex designs and AI/ML architectures, as well as high-speed interfaces and mixed-signal systems.
What You’ll Do
- Assist on verification strategies, plans, environments, and schedules for complex ASIC, SoC, and FPGA designs.
- Develop reusable UVM-based verification environments using SystemVerilog.
- Create constrained-random, directed, assertion-based, formal, and semi-formal verification methodologies.
- Develop scoreboards, monitors, drivers, checkers, assertions, reference models, and functional coverage models.
- Assist on functional and code coverage analysis, closure, and verification signoff.
- Build and maintain automated regression infrastructure using Python, Tcl, Perl, shell scripting, Jenkins, Git, and CI/CD pipelines.
- Verify RTL and gate-level designs across simulation, emulation, FPGA prototyping, and post-silicon environments.
- Debug complex issues across RTL, testbenches, gate-level netlists, timing models, and system-level platforms.
- Perform root-cause analysis and collaborate with design, architecture, physical design, firmware, and system teams to resolve defects.
- Validate performance and functionality across interfaces including AMBA, PCIe, DDR, MIPI, Ethernet, SerDes, SPI, I²C, and UART.
- Support clock-domain crossing, low-power, reset, timing, and mixed-signal interface verification.
- Correlate simulation, emulation, lab, and post-silicon results to improve verification quality and product performance.
- Contribute to verification methodology, automation, KPI frameworks, and continuous process improvement.
Join our Team
What You'll Bring.
- Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
- Six or more years of experience in design verification for ASIC, SoC, FPGA, or related semiconductor products.
- Strong programming experience with SystemVerilog and Verilog.
- Hands-on expertise developing and maintaining UVM-based verification environments.
- Experience with constrained-random verification, assertion-based verification, scoreboards, checkers, and coverage-driven verification.
- Some experience in functional and code coverage closure.
- Strong scripting and automation skills using one or more of Python, Tcl, Perl, or shell scripting.
- Experience debugging RTL and gate-level simulations and performing detailed root-cause analysis.
- A basic understanding of SoC architectures and one or more of the following: RISC-V, ARM Cortex, GPU, DSP, ISP, or AI/ML accelerators.
- Experience verifying standard interfaces and protocols such as AMBA AXI/AHB/APB, PCIe, DDR, MIPI, Ethernet, SPI, I²C, UART, or SerDes.
- Strong written and verbal communication skills.
- Demonstrated ability to collaborate effectively across architecture, design, firmware, validation, and systems engineering teams.
Desired Qualifications
- Experience with formal or semi-formal verification using tools such as JasperGold or equivalent.
- Experience with mixed-signal designs, high-speed I/O, or RF-related validation.
- Knowledge of clock-domain crossing, reset-domain crossing, low-power verification, UPF, or CPF.
- Experience with emulation, FPGA prototyping, or post-silicon validation.
- Familiarity with PCIe, DDR3/4/5, MIPI CSI/DSI, SerDes, or other high-speed interfaces.
- Experience with timing closure, performance analysis, or simulation-to-silicon correlation.
- Exposure to RISC-V or ARM assembly and C/C++-based verification.
- Experience using tools such as Synopsys VCS, Verdi, DVE, SpyGlass, Cadence Xcelium, SimVision, Mentor Questa/ModelSim, Riviera-PRO, Vivado, or Intel Quartus.
- Familiarity with Jira, Confluence, Git, Jenkins, and Agile development practices.
- Experience with LabVIEW, software-defined radio systems, spectrum analyzers, or network analyzers.
- Previous experience mentoring verification engineers or leading verification activities.
Why Join Ericsson Silicon?
You will work on challenging silicon programs where verification quality directly influences product success. From reusable verification infrastructure to post-silicon debug, your work will help ensure that complex ASIC and SoC designs perform reliably in demanding real-world environments.
Join a team where you can combine deep technical expertise, creative problem-solving, and leadership to improve how high-performance silicon is designed, verified, and brought to market.
What happens once you apply?
Click Here to find all you need to know about what our typical hiring process looks like.
Ericsson uses a merit-based hiring approach that values people with different experiences, perspectives and skillsets. We truly believe this approach drives innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity employer, learn more.
If you need assistance or to request an accommodation due to a disability, please contact Ericsson at hr.direct.americas@ericsson.com.
DISCLAIMER: The above statements are intended to describe the general nature and level of work being performed by employees in this position. They are not an exhaustive list of all responsibilities, duties and skills required for this position, and you may be required to perform additional job tasks as assigned.
Primary country and city: USA || Austin, Texas
Job details: Developer
Primary Recruiter: Jim Everett
Compensation and Benefits at Ericsson
At Ericsson, we know that our people are the key to our success. We offer a competitive package to help with your individual needs and goals.
Your Pay
The salary range for this position is dependent on various factors including, but not limited to, location, and the candidate’s combination of job-related knowledge, qualifications, skills, education, training, and experience.
Short-Term Variable Compensation Plan: Your pay also includes the opportunity for an annual bonus. Actual bonus payouts are based on performance of the business against the unit’s objectives, individual performance, and the individual bonus target. Certain eligibility and pro-ration rules apply.
Your Health
Ericsson offers excellent health benefits including the choice of three medical plan options and a dental plan option that allow an employee to select the level of coverage that suits their needs. Employees will receive company credits in an amount equal to the cost that Ericsson pays toward the cost of their medical and dental premiums for themselves and eligible covered dependents.
Your Financial Security
We invest in both your short and long-term financial wellbeing. The Ericsson US 401(k) Plan offers an automatic 3% company contribution and Ericsson match $1 for every $1 you put into the 401(k) Plan on the first 3% of your eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay. When you contribute at least 5% of eligible pay, you are receiving Ericsson’s full matching contributions of 4%. Matching and company automatic contributions stop when your total eligible pay for the year reaches the IRS limits. Employees will also receive company credits in an amount equal to the cost of basic life insurance and basic accidental death and dismemberment coverage, as well as short-term and long-term disability coverage. Employees also have the option to participate in Ericsson’s Stock Purchase Plan.
Your Time
Your work-life balance is important to us. New employees are provided a minimum of 15 days of accrued vacation, up to 3 personal days per year, 11 annual holidays, 8 hours of volunteer time, and 80 hours of sick time annually. Please note paid time off is pro-rated based on the employee’s start date. Furthermore, Ericsson provides up to 16 weeks of paid maternity leave and 6 weeks of parental or adoption leave at 100% of pay.
Additional Benefits
Ericsson offers many other company-paid benefits such as financial wellness programs, educational assistance, matching gifts, and recognition programs.
Grow with us
About this opportunity:
Design Verification Engineer
ASIC, SoC & FPGA Verification | Ericsson Silicon | Austin, Texas
Build the Verification Foundation for Next-Generation Silicon.
Ericsson Silicon is looking for a results-driven Design Verification Engineer to help develop and validate the ASICs, SoCs, and FPGA-based platforms powering next-generation communications infrastructure.
In this role, you will contribute to verification activities across the product lifecycle—from testbench architecture and constrained-random verification through coverage closure, regression automation, gate-level validation, and post-silicon correlation. You will work closely with architects, RTL designers, emulation teams, and system engineers to identify issues early, accelerate tapeout, and deliver high-quality silicon.
This is an opportunity to make a direct impact on complex designs and AI/ML architectures, as well as high-speed interfaces and mixed-signal systems.
What You’ll Do
- Assist on verification strategies, plans, environments, and schedules for complex ASIC, SoC, and FPGA designs.
- Develop reusable UVM-based verification environments using SystemVerilog.
- Create constrained-random, directed, assertion-based, formal, and semi-formal verification methodologies.
- Develop scoreboards, monitors, drivers, checkers, assertions, reference models, and functional coverage models.
- Assist on functional and code coverage analysis, closure, and verification signoff.
- Build and maintain automated regression infrastructure using Python, Tcl, Perl, shell scripting, Jenkins, Git, and CI/CD pipelines.
- Verify RTL and gate-level designs across simulation, emulation, FPGA prototyping, and post-silicon environments.
- Debug complex issues across RTL, testbenches, gate-level netlists, timing models, and system-level platforms.
- Perform root-cause analysis and collaborate with design, architecture, physical design, firmware, and system teams to resolve defects.
- Validate performance and functionality across interfaces including AMBA, PCIe, DDR, MIPI, Ethernet, SerDes, SPI, I²C, and UART.
- Support clock-domain crossing, low-power, reset, timing, and mixed-signal interface verification.
- Correlate simulation, emulation, lab, and post-silicon results to improve verification quality and product performance.
- Contribute to verification methodology, automation, KPI frameworks, and continuous process improvement.
Join our Team
What You'll Bring.
- Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
- Six or more years of experience in design verification for ASIC, SoC, FPGA, or related semiconductor products.
- Strong programming experience with SystemVerilog and Verilog.
- Hands-on expertise developing and maintaining UVM-based verification environments.
- Experience with constrained-random verification, assertion-based verification, scoreboards, checkers, and coverage-driven verification.
- Some experience in functional and code coverage closure.
- Strong scripting and automation skills using one or more of Python, Tcl, Perl, or shell scripting.
- Experience debugging RTL and gate-level simulations and performing detailed root-cause analysis.
- A basic understanding of SoC architectures and one or more of the following: RISC-V, ARM Cortex, GPU, DSP, ISP, or AI/ML accelerators.
- Experience verifying standard interfaces and protocols such as AMBA AXI/AHB/APB, PCIe, DDR, MIPI, Ethernet, SPI, I²C, UART, or SerDes.
- Strong written and verbal communication skills.
- Demonstrated ability to collaborate effectively across architecture, design, firmware, validation, and systems engineering teams.
Desired Qualifications
- Experience with formal or semi-formal verification using tools such as JasperGold or equivalent.
- Experience with mixed-signal designs, high-speed I/O, or RF-related validation.
- Knowledge of clock-domain crossing, reset-domain crossing, low-power verification, UPF, or CPF.
- Experience with emulation, FPGA prototyping, or post-silicon validation.
- Familiarity with PCIe, DDR3/4/5, MIPI CSI/DSI, SerDes, or other high-speed interfaces.
- Experience with timing closure, performance analysis, or simulation-to-silicon correlation.
- Exposure to RISC-V or ARM assembly and C/C++-based verification.
- Experience using tools such as Synopsys VCS, Verdi, DVE, SpyGlass, Cadence Xcelium, SimVision, Mentor Questa/ModelSim, Riviera-PRO, Vivado, or Intel Quartus.
- Familiarity with Jira, Confluence, Git, Jenkins, and Agile development practices.
- Experience with LabVIEW, software-defined radio systems, spectrum analyzers, or network analyzers.
- Previous experience mentoring verification engineers or leading verification activities.
Why Join Ericsson Silicon?
You will work on challenging silicon programs where verification quality directly influences product success. From reusable verification infrastructure to post-silicon debug, your work will help ensure that complex ASIC and SoC designs perform reliably in demanding real-world environments.
Join a team where you can combine deep technical expertise, creative problem-solving, and leadership to improve how high-performance silicon is designed, verified, and brought to market.
What happens once you apply?
Click Here to find all you need to know about what our typical hiring process looks like.
Ericsson uses a merit-based hiring approach that values people with different experiences, perspectives and skillsets. We truly believe this approach drives innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity employer, learn more.
If you need assistance or to request an accommodation due to a disability, please contact Ericsson at hr.direct.americas@ericsson.com.
DISCLAIMER: The above statements are intended to describe the general nature and level of work being performed by employees in this position. They are not an exhaustive list of all responsibilities, duties and skills required for this position, and you may be required to perform additional job tasks as assigned.
Primary country and city: USA || Austin, Texas
Job details: Developer
Primary Recruiter: Jim Everett
Compensation and Benefits at Ericsson
At Ericsson, we know that our people are the key to our success. We offer a competitive package to help with your individual needs and goals.
Your Pay
The salary range for this position is dependent on various factors including, but not limited to, location, and the candidate’s combination of job-related knowledge, qualifications, skills, education, training, and experience.
Short-Term Variable Compensation Plan: Your pay also includes the opportunity for an annual bonus. Actual bonus payouts are based on performance of the business against the unit’s objectives, individual performance, and the individual bonus target. Certain eligibility and pro-ration rules apply.
Your Health
Ericsson offers excellent health benefits including the choice of three medical plan options and a dental plan option that allow an employee to select the level of coverage that suits their needs. Employees will receive company credits in an amount equal to the cost that Ericsson pays toward the cost of their medical and dental premiums for themselves and eligible covered dependents.
Your Financial Security
We invest in both your short and long-term financial wellbeing. The Ericsson US 401(k) Plan offers an automatic 3% company contribution and Ericsson match $1 for every $1 you put into the 401(k) Plan on the first 3% of your eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay. When you contribute at least 5% of eligible pay, you are receiving Ericsson’s full matching contributions of 4%. Matching and company automatic contributions stop when your total eligible pay for the year reaches the IRS limits. Employees will also receive company credits in an amount equal to the cost of basic life insurance and basic accidental death and dismemberment coverage, as well as short-term and long-term disability coverage. Employees also have the option to participate in Ericsson’s Stock Purchase Plan.
Your Time
Your work-life balance is important to us. New employees are provided a minimum of 15 days of accrued vacation, up to 3 personal days per year, 11 annual holidays, 8 hours of volunteer time, and 80 hours of sick time annually. Please note paid time off is pro-rated based on the employee’s start date. Furthermore, Ericsson provides up to 16 weeks of paid maternity leave and 6 weeks of parental or adoption leave at 100% of pay.
Additional Benefits
Ericsson offers many other company-paid benefits such as financial wellness programs, educational assistance, matching gifts, and recognition programs.
See all 1,202+ Senior Asic Design Engineer Jobs
Sign up for free to unlock all listings, filter by visa type, and get alerts for new Senior Asic Design Engineer roles.
Get Access To All JobsTips for Finding Visa Sponsorship as a Senior Asic Design Engineer
Target semiconductor-heavy hiring hubs
Companies in San Jose, Austin, and Raleigh file the most LCAs for ASIC design roles. Concentrating your search on these metros increases your chances of finding employers with established visa sponsorship infrastructure and dedicated immigration counsel.
Lead with tape-out experience on your resume
USCIS adjudicators and employers both want evidence of specialized expertise. Listing specific process nodes, tape-out counts, and EDA tools used signals the depth required for H-1B specialty occupation approval and sets you apart from general chip designers.
Understand your degree field matters as much as level
USCIS requires a bachelor's degree in a directly related field for H-1B specialty occupation approval. Electrical engineering, computer engineering, or microelectronics degrees align well. A business or general IT degree may trigger a Request for Evidence even with strong experience.
Large fabless and IDM companies sponsor most consistently
Established semiconductor firms like Qualcomm, Intel, Nvidia, and Broadcom have mature H-1B sponsorship programs and dedicated legal teams. Smaller startups may intend to sponsor but lack the infrastructure, which can cause costly delays during petition preparation.
Request premium processing to reduce hiring uncertainty
Employers can pay for premium processing on your H-1B petition, cutting USCIS review to 15 business days. For ASIC roles with defined project timelines and tapeout schedules, this removes months of uncertainty and is standard practice at most semiconductor companies.
Document your contributions at the system architecture level
Senior ASIC roles that involve microarchitecture decisions, cross-functional leadership, or IP development strengthen O-1A extraordinary ability petitions. Gather evidence of patents filed, conference presentations, and peer recognition now, even if you're currently pursuing H-1B sponsorship.
Frequently Asked Questions
Is Senior ASIC Design Engineer a qualifying specialty occupation for H-1B?
Yes. Senior ASIC Design Engineer is one of the more straightforward H-1B visa specialty occupation approvals. USCIS consistently recognizes the role as requiring at least a bachelor's degree in electrical engineering, computer engineering, or a closely related field. RTL design, physical design, and verification subfields all qualify. Roles blending general project management with minimal engineering work can face scrutiny, so the job description should emphasize technical depth.
Which visa types do ASIC engineering employers typically sponsor?
H-1B is the most common, followed by O-1A for engineers with patents, publications, or industry awards demonstrating extraordinary ability. L-1A and L-1B transfers are available for engineers moving from a foreign affiliate of a U.S. employer. Australian citizens can use the E-3 visa, which has no lottery and is far easier to obtain. Browse visa-sponsored ASIC roles across all these categories on Migrate Mate.
Does my three-year engineering degree qualify for an H-1B as an ASIC engineer?
It depends on the country and degree evaluator. USCIS accepts a three-year bachelor's degree combined with a one-year U.S. master's program or additional post-secondary coursework as equivalent to a four-year U.S. degree. Indian three-year B.Tech degrees paired with a U.S. master's are routinely accepted. A standalone three-year degree without additional credentials can trigger a Request for Evidence and should be supported by a credential evaluation from a NACES-accredited agency.
How does the H-1B lottery affect ASIC engineering job offers?
H-1B cap-subject petitions enter the annual lottery held each April, with roughly a 25% selection rate in recent years. If not selected, employment cannot begin until the following October at the earliest. Many semiconductor employers cap-exempt candidates by placing them at qualifying research institutions or university-affiliated labs. If you're on OPT or STEM OPT, your employer can file for the next lottery while you continue working legally.
What makes an ASIC engineer a strong O-1A candidate?
USCIS evaluates O-1A petitions on evidence of extraordinary ability across criteria including patents, published research, critical employment at distinguished organizations, high compensation relative to peers, and judging others' work in the field. Senior ASIC engineers who have led chip designs shipped in consumer products, hold patents, or have spoken at IEEE or DAC conferences often meet three or more criteria. An immigration attorney experienced with engineering O-1As can identify which evidence to prioritize.
What is the prevailing wage requirement for sponsored Senior Asic Design Engineer jobs?
U.S. employers sponsoring a visa must pay at least the prevailing wage, which is what workers in the same role, area, and experience level typically earn. The Department of Labor sets this rate to make sure companies aren't hiring foreign workers simply because they'd accept lower pay than a U.S. worker. It varies by job title, location, and experience. You can look up current prevailing wage rates for any occupation and location using the OFLC Wage Search page.