Senior Asic Design Engineer Jobs in USA with Visa Sponsorship
Senior ASIC Design Engineer roles attract strong H-1B visa and O-1 visa sponsorship from semiconductor and defense companies. Employers filing LCAs for this specialty occupation regularly sponsor experienced engineers with RTL, synthesis, and timing closure expertise. For detailed occupation requirements, see the O*NET profile.
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Get Access To All JobsThe application window is expected to close on: 09/25/2026. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
This Hardware Engineering position is located in San Jose, CA, and is open to remote applicants residing within the United States.
Meet the Team
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Cisco Silicon One (#CiscoSiliconOne) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.
We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large-scale integration, using the latest signaling and data transfer technologies. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry!
Your Impact
We are seeking a highly qualified Signal and Power Integrity Technical Lead to help us develop our next generation ASIC packaging to help define, design and verify ASIC packaging to be deployed in a range of Cisco platforms.
- Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
- Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
- Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
- Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
- Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments.
- Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs.
- Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met.
- Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams.
Minimum Qualifications
- Bachelor's degree in Electrical Engineering and 8+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 6+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 3+ years of relevant signal and power integrity experience.
- High-Speed Architecture & Theory: Expertise in high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
- SI/PI Simulation Proficiency: Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
- Layout Review & Physical Validation: Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and crosstalk mitigation.
- Circuit Analysis: Working knowledge of SPICE for circuit-level analysis, signal modeling, and performance validation.
Preferred Qualifications
- Skilled in articulating ideas and technical concepts to diverse audiences, both verbally and in writing.
- Experience with high-bandwidth memory (HBM) or high-speed memory interface SI.
- Experience with die-to-die interfaces (UCIe or proprietary).
- Experience with advanced packaging (CoWoS, EMIB, interposer-based designs), including SI/PI analysis of 2.5D ASIC packaging.
- Working knowledge of Vector Network Analysis.
- Basic knowledge of IBIS.
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Message to applicants applying to work in the U.S. and/or Canada:
The starting salary range posted for this position is $183,800.00 to $263,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.
U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:
- 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
- Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
- Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
- 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:
- .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
- 1.5% of incentive target for each 1% of attainment between 50% and 75%;
- 1% of incentive target for each 1% of attainment between 75% and 100%; and
- Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.
The applicable full salary ranges for this position, by specific state, are listed below:
New York City Metro Area:
$183,800.00 - $303,100.00
Non-Metro New York state & Washington state:
$163,600.00 - $269,800.00
- For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.
The application window is expected to close on: 09/25/2026. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
This Hardware Engineering position is located in San Jose, CA, and is open to remote applicants residing within the United States.
Meet the Team
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Cisco Silicon One (#CiscoSiliconOne) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.
We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large-scale integration, using the latest signaling and data transfer technologies. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry!
Your Impact
We are seeking a highly qualified Signal and Power Integrity Technical Lead to help us develop our next generation ASIC packaging to help define, design and verify ASIC packaging to be deployed in a range of Cisco platforms.
- Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
- Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
- Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
- Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
- Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments.
- Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs.
- Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met.
- Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams.
Minimum Qualifications
- Bachelor's degree in Electrical Engineering and 8+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 6+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 3+ years of relevant signal and power integrity experience.
- High-Speed Architecture & Theory: Expertise in high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
- SI/PI Simulation Proficiency: Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
- Layout Review & Physical Validation: Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and crosstalk mitigation.
- Circuit Analysis: Working knowledge of SPICE for circuit-level analysis, signal modeling, and performance validation.
Preferred Qualifications
- Skilled in articulating ideas and technical concepts to diverse audiences, both verbally and in writing.
- Experience with high-bandwidth memory (HBM) or high-speed memory interface SI.
- Experience with die-to-die interfaces (UCIe or proprietary).
- Experience with advanced packaging (CoWoS, EMIB, interposer-based designs), including SI/PI analysis of 2.5D ASIC packaging.
- Working knowledge of Vector Network Analysis.
- Basic knowledge of IBIS.
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Message to applicants applying to work in the U.S. and/or Canada:
The starting salary range posted for this position is $183,800.00 to $263,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.
U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:
- 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
- Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
- Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
- 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:
- .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
- 1.5% of incentive target for each 1% of attainment between 50% and 75%;
- 1% of incentive target for each 1% of attainment between 75% and 100%; and
- Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.
The applicable full salary ranges for this position, by specific state, are listed below:
New York City Metro Area:
$183,800.00 - $303,100.00
Non-Metro New York state & Washington state:
$163,600.00 - $269,800.00
- For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.
See all 1,467+ Senior Asic Design Engineer Jobs
Sign up for free to unlock all listings, filter by visa type, and get alerts for new Senior Asic Design Engineer roles.
Get Access To All JobsTips for Finding Visa Sponsorship as a Senior Asic Design Engineer
Target semiconductor-heavy hiring hubs
Companies in San Jose, Austin, and Raleigh file the most LCAs for ASIC design roles. Concentrating your search on these metros increases your chances of finding employers with established visa sponsorship infrastructure and dedicated immigration counsel.
Lead with tape-out experience on your resume
USCIS adjudicators and employers both want evidence of specialized expertise. Listing specific process nodes, tape-out counts, and EDA tools used signals the depth required for H-1B specialty occupation approval and sets you apart from general chip designers.
Understand your degree field matters as much as level
USCIS requires a bachelor's degree in a directly related field for H-1B specialty occupation approval. Electrical engineering, computer engineering, or microelectronics degrees align well. A business or general IT degree may trigger a Request for Evidence even with strong experience.
Large fabless and IDM companies sponsor most consistently
Established semiconductor firms like Qualcomm, Intel, Nvidia, and Broadcom have mature H-1B sponsorship programs and dedicated legal teams. Smaller startups may intend to sponsor but lack the infrastructure, which can cause costly delays during petition preparation.
Request premium processing to reduce hiring uncertainty
Employers can pay for premium processing on your H-1B petition, cutting USCIS review to 15 business days. For ASIC roles with defined project timelines and tapeout schedules, this removes months of uncertainty and is standard practice at most semiconductor companies.
Document your contributions at the system architecture level
Senior ASIC roles that involve microarchitecture decisions, cross-functional leadership, or IP development strengthen O-1A extraordinary ability petitions. Gather evidence of patents filed, conference presentations, and peer recognition now, even if you're currently pursuing H-1B sponsorship.
Frequently Asked Questions
Is Senior ASIC Design Engineer a qualifying specialty occupation for H-1B?
Yes. Senior ASIC Design Engineer is one of the more straightforward H-1B visa specialty occupation approvals. USCIS consistently recognizes the role as requiring at least a bachelor's degree in electrical engineering, computer engineering, or a closely related field. RTL design, physical design, and verification subfields all qualify. Roles blending general project management with minimal engineering work can face scrutiny, so the job description should emphasize technical depth.
Which visa types do ASIC engineering employers typically sponsor?
H-1B is the most common, followed by O-1A for engineers with patents, publications, or industry awards demonstrating extraordinary ability. L-1A and L-1B transfers are available for engineers moving from a foreign affiliate of a U.S. employer. Australian citizens can use the E-3 visa, which has no lottery and is far easier to obtain. Browse visa-sponsored ASIC roles across all these categories on Migrate Mate.
Does my three-year engineering degree qualify for an H-1B as an ASIC engineer?
It depends on the country and degree evaluator. USCIS accepts a three-year bachelor's degree combined with a one-year U.S. master's program or additional post-secondary coursework as equivalent to a four-year U.S. degree. Indian three-year B.Tech degrees paired with a U.S. master's are routinely accepted. A standalone three-year degree without additional credentials can trigger a Request for Evidence and should be supported by a credential evaluation from a NACES-accredited agency.
How does the H-1B lottery affect ASIC engineering job offers?
H-1B cap-subject petitions enter the annual lottery held each April, with roughly a 25% selection rate in recent years. If not selected, employment cannot begin until the following October at the earliest. Many semiconductor employers cap-exempt candidates by placing them at qualifying research institutions or university-affiliated labs. If you're on OPT or STEM OPT, your employer can file for the next lottery while you continue working legally.
What makes an ASIC engineer a strong O-1A candidate?
USCIS evaluates O-1A petitions on evidence of extraordinary ability across criteria including patents, published research, critical employment at distinguished organizations, high compensation relative to peers, and judging others' work in the field. Senior ASIC engineers who have led chip designs shipped in consumer products, hold patents, or have spoken at IEEE or DAC conferences often meet three or more criteria. An immigration attorney experienced with engineering O-1As can identify which evidence to prioritize.
What is the prevailing wage requirement for sponsored Senior Asic Design Engineer jobs?
U.S. employers sponsoring a visa must pay at least the prevailing wage, which is what workers in the same role, area, and experience level typically earn. The Department of Labor sets this rate to make sure companies aren't hiring foreign workers simply because they'd accept lower pay than a U.S. worker. It varies by job title, location, and experience. You can look up current prevailing wage rates for any occupation and location using the OFLC Wage Search page.