Senior Asic Design Engineer Jobs in USA with Visa Sponsorship
Senior ASIC Design Engineer roles attract strong H-1B visa and O-1 visa sponsorship from semiconductor and defense companies. Employers filing LCAs for this specialty occupation regularly sponsor experienced engineers with RTL, synthesis, and timing closure expertise. For detailed occupation requirements, see the O*NET profile.
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INTRODUCTION
At Cornelis we’re building the future of AI and HPC networking with an AI-first approach to silicon and software development. We’re seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.
Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions.
We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles.
ROLE AND RESPONSIBILITIES
Cornelis Networks is seeking talented Senior ASIC Design Engineers with deep expertise in one or more of the critical areas needed to develop world-class SoCs for deployment in high-performance computing, advanced data analytics, and AI interconnect solutions. Ideal candidates will have relevant experience in the networking domain, with proven expertise in 50G, 100G, and 400G Ethernet protocols—including TCP/IP, RDMA/RoCE, and IPSec—and their application in high-speed data processing and networking environments.
Key Responsibilities:
- Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing logic.
- Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage.
- Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure.
- Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues.
- Contribute to performance optimization and power-aware design strategies for Host Fabric Interface subsystems.
MINIMUM QUALIFICATIONS
- B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field.
- 8+ years of post-college experience in digital design with proficiency in Verilog and System Verilog.
- Experience in RTL design for high-speed data paths or packet processing in ASICs.
- Deep understanding of Host Ethernet adaptor architectures.
- Familiarity with timing closure and modern physical design methodologies.
- Proven ability in system-level debug and root cause analysis of technical issues.
- Strong verbal and written communication skills.
PREFERRED QUALIFICATIONS
- Knowledge of Ethernet architecture and networking protocols.
- Prior experience with RTL development for Ethernet host adapters and system debug.
- Expertise in multiple clock domain designs and asynchronous interfaces.
- 5+ years of experience with scripting languages such as TCL, Python, or Perl.
- Familiarity with EDA tools like Design Compiler, Spyglass, or PrimeTime.
LOCATION
This is a remote position for employees residing within the United States.
We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry.
At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives.
In addition to your base pay, you’ll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave.
Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
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Get Access To All JobsTips for Finding Visa Sponsorship as a Senior Asic Design Engineer
Target semiconductor-heavy hiring hubs
Companies in San Jose, Austin, and Raleigh file the most LCAs for ASIC design roles. Concentrating your search on these metros increases your chances of finding employers with established visa sponsorship infrastructure and dedicated immigration counsel.
Lead with tape-out experience on your resume
USCIS adjudicators and employers both want evidence of specialized expertise. Listing specific process nodes, tape-out counts, and EDA tools used signals the depth required for H-1B specialty occupation approval and sets you apart from general chip designers.
Understand your degree field matters as much as level
USCIS requires a bachelor's degree in a directly related field for H-1B specialty occupation approval. Electrical engineering, computer engineering, or microelectronics degrees align well. A business or general IT degree may trigger a Request for Evidence even with strong experience.
Large fabless and IDM companies sponsor most consistently
Established semiconductor firms like Qualcomm, Intel, Nvidia, and Broadcom have mature H-1B sponsorship programs and dedicated legal teams. Smaller startups may intend to sponsor but lack the infrastructure, which can cause costly delays during petition preparation.
Request premium processing to reduce hiring uncertainty
Employers can pay for premium processing on your H-1B petition, cutting USCIS review to 15 business days. For ASIC roles with defined project timelines and tapeout schedules, this removes months of uncertainty and is standard practice at most semiconductor companies.
Document your contributions at the system architecture level
Senior ASIC roles that involve microarchitecture decisions, cross-functional leadership, or IP development strengthen O-1A extraordinary ability petitions. Gather evidence of patents filed, conference presentations, and peer recognition now, even if you're currently pursuing H-1B sponsorship.
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Find Senior Asic Design Engineer JobsFrequently Asked Questions
Is Senior ASIC Design Engineer a qualifying specialty occupation for H-1B?
Yes. Senior ASIC Design Engineer is one of the more straightforward H-1B specialty occupation approvals. USCIS consistently recognizes the role as requiring at least a bachelor's degree in electrical engineering, computer engineering, or a closely related field. RTL design, physical design, and verification subfields all qualify. Roles blending general project management with minimal engineering work can face scrutiny, so the job description should emphasize technical depth.
Which visa types do ASIC engineering employers typically sponsor?
H-1B is the most common, followed by O-1A for engineers with patents, publications, or industry awards demonstrating extraordinary ability. L-1A and L-1B transfers are available for engineers moving from a foreign affiliate of a U.S. employer. Australian citizens can use the E-3, which has no lottery and is far easier to obtain. Browse visa-sponsored ASIC roles across all these categories on Migrate Mate.
Does my three-year engineering degree qualify for an H-1B as an ASIC engineer?
It depends on the country and degree evaluator. USCIS accepts a three-year bachelor's degree combined with a one-year U.S. master's program or additional post-secondary coursework as equivalent to a four-year U.S. degree. Indian three-year B.Tech degrees paired with a U.S. master's are routinely accepted. A standalone three-year degree without additional credentials can trigger a Request for Evidence and should be supported by a credential evaluation from a NACES-accredited agency.
How does the H-1B lottery affect ASIC engineering job offers?
H-1B cap-subject petitions enter the annual lottery held each April, with roughly a 25% selection rate in recent years. If not selected, employment cannot begin until the following October at the earliest. Many semiconductor employers cap-exempt candidates by placing them at qualifying research institutions or university-affiliated labs. If you're on OPT or STEM OPT, your employer can file for the next lottery while you continue working legally.
What makes an ASIC engineer a strong O-1A candidate?
USCIS evaluates O-1A petitions on evidence of extraordinary ability across criteria including patents, published research, critical employment at distinguished organizations, high compensation relative to peers, and judging others' work in the field. Senior ASIC engineers who have led chip designs shipped in consumer products, hold patents, or have spoken at IEEE or DAC conferences often meet three or more criteria. An immigration attorney experienced with engineering O-1As can identify which evidence to prioritize.
What is the prevailing wage requirement for sponsored Senior Asic Design Engineer jobs?
U.S. employers sponsoring a visa must pay at least the prevailing wage, which is what workers in the same role, area, and experience level typically earn. The Department of Labor sets this rate to make sure companies aren't hiring foreign workers simply because they'd accept lower pay than a U.S. worker. It varies by job title, location, and experience. You can look up current prevailing wage rates for any occupation and location using the OFLC Wage Search page.
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