CPT Design Verification Jobs
Design Verification CPT roles place F-1 students inside hardware validation pipelines, running functional and timing simulations before a chip or system ships. Your DSO must authorize CPT as part of your degree plan, and the work must tie directly to your enrolled coursework, so Engineering or ECE students fit this role cleanly.
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Get Access To All JobsINTRODUCTION
Altera is seeking a highly motivated Graduate Intern to join our FPGA Digital Design and Verification team. This internship provides hands-on experience working on industry-leading programmable logic devices, SoC platforms, and verification environments. The role is ideal for graduate students eager to grow their expertise in SystemVerilog, UVM-based verification, and digital design methodologies.
You will collaborate with experienced engineers to design, verify, and validate RTL blocks and system-level features used in next-generation FPGA products.
ROLE AND RESPONSIBILITIES
- Develop and maintain SystemVerilog/UVM-based verification environments for FPGA IPs and subsystems
- Create self-checking testbenches, constrained-random tests, and functional coverage models
- Write and debug SystemVerilog Assertions (SVA) to ensure protocol and design correctness
- Execute and analyze simulations using industry-standard EDA tools (VCS, QuestaSim, ModelSim)
- Assist in debugging RTL and verification failures, working closely with design engineers
- Verify common communication protocols (e.g., UART, SPI) and custom interconnects
- Contribute to documentation of verification plans, test strategies, and results
- Support FPGA-based systems including AI/ML accelerators, memory interfaces, and SoC components
BASIC QUALIFICATIONS
- Currently pursuing a Graduate Degree in Computer or Electrical Engineering or related field
- Strong foundation in Digital Logic Design and Computer Architecture
- Proficiency in SystemVerilog and Verilog
- Knowledge of UVM, functional coverage, constrained random verification, and assertions
- Experience using simulation and verification tools such as ModelSim, QuestaSim, or Synopsys VCS
- Familiarity with Linux-based development environments
- Ability to debug simulation issues and analyze waveforms effectively
PREFERRED QUALIFICATIONS
- Hands-on project experience with UVM-based verification environments
- Experience verifying communication protocols (UART, SPI, AXI preferred)
- Exposure to FPGA tools such as Intel Quartus Prime or Xilinx Vivado
- Knowledge of SVA or formal verification concepts
- Programming or scripting experience in Python, Perl, Tcl, or C
- Exposure to HLS, SoC design, or hardware acceleration for AI/ML workloads
COMPENSATION
- Salary Range: $95K - $100K USD
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
JOB TYPE
Student / Intern (Fixed Term)
SHIFT
Shift 1 (United States of America)
LOCATION
Primary Location: San Jose, California, United States
POSTING STATEMENT
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
INTRODUCTION
Altera is seeking a highly motivated Graduate Intern to join our FPGA Digital Design and Verification team. This internship provides hands-on experience working on industry-leading programmable logic devices, SoC platforms, and verification environments. The role is ideal for graduate students eager to grow their expertise in SystemVerilog, UVM-based verification, and digital design methodologies.
You will collaborate with experienced engineers to design, verify, and validate RTL blocks and system-level features used in next-generation FPGA products.
ROLE AND RESPONSIBILITIES
- Develop and maintain SystemVerilog/UVM-based verification environments for FPGA IPs and subsystems
- Create self-checking testbenches, constrained-random tests, and functional coverage models
- Write and debug SystemVerilog Assertions (SVA) to ensure protocol and design correctness
- Execute and analyze simulations using industry-standard EDA tools (VCS, QuestaSim, ModelSim)
- Assist in debugging RTL and verification failures, working closely with design engineers
- Verify common communication protocols (e.g., UART, SPI) and custom interconnects
- Contribute to documentation of verification plans, test strategies, and results
- Support FPGA-based systems including AI/ML accelerators, memory interfaces, and SoC components
BASIC QUALIFICATIONS
- Currently pursuing a Graduate Degree in Computer or Electrical Engineering or related field
- Strong foundation in Digital Logic Design and Computer Architecture
- Proficiency in SystemVerilog and Verilog
- Knowledge of UVM, functional coverage, constrained random verification, and assertions
- Experience using simulation and verification tools such as ModelSim, QuestaSim, or Synopsys VCS
- Familiarity with Linux-based development environments
- Ability to debug simulation issues and analyze waveforms effectively
PREFERRED QUALIFICATIONS
- Hands-on project experience with UVM-based verification environments
- Experience verifying communication protocols (UART, SPI, AXI preferred)
- Exposure to FPGA tools such as Intel Quartus Prime or Xilinx Vivado
- Knowledge of SVA or formal verification concepts
- Programming or scripting experience in Python, Perl, Tcl, or C
- Exposure to HLS, SoC design, or hardware acceleration for AI/ML workloads
COMPENSATION
- Salary Range: $95K - $100K USD
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
JOB TYPE
Student / Intern (Fixed Term)
SHIFT
Shift 1 (United States of America)
LOCATION
Primary Location: San Jose, California, United States
POSTING STATEMENT
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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Get Access To All JobsDesign Verification CPT: Frequently Asked Questions
Does Design Verification work qualify as CPT for ECE and CS students?
Yes, if your program includes coursework in digital design, verification methodology, or hardware engineering. Your DSO will require you to show a direct academic connection between your enrolled courses and the job duties. Roles involving SystemVerilog, UVM testbench development, or RTL simulation typically satisfy this requirement for ECE and CS degree programs.
Can I do full-time CPT in a Design Verification role without losing OPT?
Full-time CPT totaling 12 or more months in aggregate eliminates your OPT eligibility. If you're not yet in your final year, part-time CPT keeps OPT intact. Discuss your cumulative CPT timeline with your DSO before accepting a full-time offer, especially if you plan to pursue STEM OPT after graduation.
How do I find Design Verification employers who are likely to sponsor visas after CPT?
Search Migrate Mate to find employers with LCA filing history for engineering and verification roles. Prior DOL filings signal that the company has sponsored F-1 students through OPT and H-1B visa before. Semiconductor, EDA, and defense electronics firms are common hirers for this role type and have established international hiring processes.
What should my offer letter include to get DSO approval for CPT?
Your offer letter needs the employer name, job title, specific start and end dates, whether the position is full-time or part-time, and a description of job duties. The duties section matters most for DSO review. Generic language like 'engineering tasks' is often rejected. Ask your employer to list specific verification responsibilities such as writing test plans, running simulations, or analyzing coverage results.
Does my CPT employer need to be E-Verify enrolled?
E-Verify enrollment is not required for CPT itself, but it becomes mandatory if you later pursue a STEM OPT extension with that same employer. Hiring at a non-E-Verify employer on CPT is permitted, but you won't be eligible for the 24-month STEM OPT extension there unless the employer enrolls before your OPT start date.