Digital Design Engineer Jobs
Digital Design Engineer jobs are open across semiconductors, aerospace, consumer electronics, and automotive, from new-grad to principal and staff levels, with specializations in RTL design, FPGA development, and ASIC verification. See the openings below and apply to the ones that match your experience.
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MaxLinear is seeking a Senior Principal Digital SoC Design Engineer to join our Analog Mixed Signal (AMS) group in San Jose, CA. The AMS team develops a broad portfolio of integrated solutions spanning high speed and embedded connectivity interfaces (bridges, serial transceivers, isolators) and power management, supporting data center, industrial, and embedded platforms. In this role, you will lead digital architecture and RTL for a roadmap of products ranging from USB-based connectivity bridges to PCIe-to-USB host bridge devices, to complex embedded-processor SoCs for data center platform management, and will focus on the following:
- Lead digital architecture and RTL for USB device-side connectivity bridges, including multi-port serial (UART), I²C/SPI/GPIO bridging, endpoint/FIFO architecture, flow control, and OTP-based configurability and customization
- Architect and integrate PCIe-to-USB host bridge solutions, including PCIe endpoint and USB host controller (xHCI) integration, DMA engines, buffer management, interrupt and power-state handling, and driver-visible register architecture
- Define and lead digital architecture for complex embedded-processor SoCs for data center platform management, including multi-core Arm subsystems, memory controllers, high speed host interfaces, sideband management buses, and peripheral-rich I/O
- Drive platform security and management features, including secure boot, hardware root of trust, cryptographic checksum generator and checker, and host-to-management communication paths
- Maximize reuse of existing digital IP across product generations, and drive make, reuse, or license decisions for USB, PCIe, and other interface controllers and PHYs
- Define on-chip interconnect, clock/reset, low-power, and DFT architecture, and own RTL quality through lint, CDC/RDC, synthesis, timing constraints, and implementation closure
- Set verification strategy with the DV team, including compliance and interoperability readiness, emulation/FPGA prototyping, and firmware/driver co-verification
- Partner closely with analog/mixed-signal, PHY, firmware, software, package, test, and applications teams from concept through silicon bring up, compliance, qualification, and production
- Mentor senior engineers, lead design reviews, and act as the digital technical authority across connectivity and SoC roadmap
- Deep hands-on expertise in SystemVerilog/Verilog RTL design, SoC micro-architecture, and complex top-level integration
- Strong working knowledge of USB 2.0/3.x device and host architectures (including xHCI) and PCIe endpoint architecture, with experience integrating licensed controller and PHY IP
- Experience with serial and peripheral interfaces (UART, I²C/I3C, SPI, GPIO) and bridge-type data paths, FIFOs, and DMA
- Experience integrating embedded Arm processor subsystems, DDR/memory controllers, bus fabrics (AMBA AXI/AHB/APB), and security IP; familiarity with data center server management concepts (e.g., eSPI, I3C, MCTP, hardware root of trust) is a strong plus
- Strong understanding of clock/reset, CDC/RDC, low-power design, timing constraints, synthesis, DFT, and physical design trade-offs
- Track record delivering multiple SoCs from architecture through tapeout, silicon bring up, compliance certification, and high-volume production
- Experience working with external design partners and IP vendors, and ability to lead technically across multiple disciplines and global teams
- BS in Electrical Engineering or related + 15 years of experience, or MS + 12 years of experience, or Ph.D. + 9 years of experience
MaxLinear's good faith estimate starting base salary range is: $200,000 to $250,000 Annually
We offer competitive benefits designed to support employee health, welfare, and retirement and some highlights are: health care benefits, 401k savings plan, Employee Stock Purchase Plan (ESPP), and paid time off.
The actual starting base salary will be determined by the match to certain role-related criteria such as educational degree(s) or equivalent, relevant work experience, skillset needed for the role, and geographic location; this is not an all-inclusive list as some roles may require unique skills or experience.
Qualified applicants will receive consideration for employment without regard to, and will not be discriminated against based on race, sex, religion, national origin, sexual orientation, gender identity, disability, or protected veteran status.
We hire the best people in the industry and engage them in some of the most exciting opportunities that connect the world we live in today. Our growth has come from innovative, bold approaches to solving some of the world’s most challenging communication technology problems in the most efficient and effective manner.
MaxLinear began by developing the world’s first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn’t achieve the extremely high-performance requirements using CMOS, but we proved them wrong and achieved enduring global market leadership with our designs. Since then, we’ve developed a full line of products that drive 4G and 5G infrastructure; enable data center, metro and long-haul optical interconnects; bring 10Gbit to the home; power the IoT revolution; and enable robust and reliable communication in harsh industrial environments. Over the years, we’ve expanded through organic growth and through several acquisitions that have perfectly complemented our existing portfolio and enabled us to deliver complete end-to-end solutions in our target markets. One such example was the acquisition of Intel’s Home Gateway Platform Division that added Wi-Fi, Ethernet, and Broadband Gateway Processor SoC technology to our connected home portfolio creating a complete and scalable platform of connectivity and access solutions to fully address our customers’ needs.
Our headquarters are in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, California; Valencia, Spain; Bangalore, India; Munich, Germany; Israel; and Singapore.
We have approximately 1,200 employees, a substantial majority of whom have engineering degrees and include masters and Ph.D. graduates from many of the premiere universities around the world. Our employees thrive on innovation, outstanding execution, outside-the-box thinking, nimbleness, and collaboration. Together, we form a high-energy business team that is focused on building the best and most innovative products on the market.
MaxLinear is seeking a Senior Principal Digital SoC Design Engineer to join our Analog Mixed Signal (AMS) group in San Jose, CA. The AMS team develops a broad portfolio of integrated solutions spanning high speed and embedded connectivity interfaces (bridges, serial transceivers, isolators) and power management, supporting data center, industrial, and embedded platforms. In this role, you will lead digital architecture and RTL for a roadmap of products ranging from USB-based connectivity bridges to PCIe-to-USB host bridge devices, to complex embedded-processor SoCs for data center platform management, and will focus on the following:
- Lead digital architecture and RTL for USB device-side connectivity bridges, including multi-port serial (UART), I²C/SPI/GPIO bridging, endpoint/FIFO architecture, flow control, and OTP-based configurability and customization
- Architect and integrate PCIe-to-USB host bridge solutions, including PCIe endpoint and USB host controller (xHCI) integration, DMA engines, buffer management, interrupt and power-state handling, and driver-visible register architecture
- Define and lead digital architecture for complex embedded-processor SoCs for data center platform management, including multi-core Arm subsystems, memory controllers, high speed host interfaces, sideband management buses, and peripheral-rich I/O
- Drive platform security and management features, including secure boot, hardware root of trust, cryptographic checksum generator and checker, and host-to-management communication paths
- Maximize reuse of existing digital IP across product generations, and drive make, reuse, or license decisions for USB, PCIe, and other interface controllers and PHYs
- Define on-chip interconnect, clock/reset, low-power, and DFT architecture, and own RTL quality through lint, CDC/RDC, synthesis, timing constraints, and implementation closure
- Set verification strategy with the DV team, including compliance and interoperability readiness, emulation/FPGA prototyping, and firmware/driver co-verification
- Partner closely with analog/mixed-signal, PHY, firmware, software, package, test, and applications teams from concept through silicon bring up, compliance, qualification, and production
- Mentor senior engineers, lead design reviews, and act as the digital technical authority across connectivity and SoC roadmap
- Deep hands-on expertise in SystemVerilog/Verilog RTL design, SoC micro-architecture, and complex top-level integration
- Strong working knowledge of USB 2.0/3.x device and host architectures (including xHCI) and PCIe endpoint architecture, with experience integrating licensed controller and PHY IP
- Experience with serial and peripheral interfaces (UART, I²C/I3C, SPI, GPIO) and bridge-type data paths, FIFOs, and DMA
- Experience integrating embedded Arm processor subsystems, DDR/memory controllers, bus fabrics (AMBA AXI/AHB/APB), and security IP; familiarity with data center server management concepts (e.g., eSPI, I3C, MCTP, hardware root of trust) is a strong plus
- Strong understanding of clock/reset, CDC/RDC, low-power design, timing constraints, synthesis, DFT, and physical design trade-offs
- Track record delivering multiple SoCs from architecture through tapeout, silicon bring up, compliance certification, and high-volume production
- Experience working with external design partners and IP vendors, and ability to lead technically across multiple disciplines and global teams
- BS in Electrical Engineering or related + 15 years of experience, or MS + 12 years of experience, or Ph.D. + 9 years of experience
MaxLinear's good faith estimate starting base salary range is: $200,000 to $250,000 Annually
We offer competitive benefits designed to support employee health, welfare, and retirement and some highlights are: health care benefits, 401k savings plan, Employee Stock Purchase Plan (ESPP), and paid time off.
The actual starting base salary will be determined by the match to certain role-related criteria such as educational degree(s) or equivalent, relevant work experience, skillset needed for the role, and geographic location; this is not an all-inclusive list as some roles may require unique skills or experience.
Qualified applicants will receive consideration for employment without regard to, and will not be discriminated against based on race, sex, religion, national origin, sexual orientation, gender identity, disability, or protected veteran status.
We hire the best people in the industry and engage them in some of the most exciting opportunities that connect the world we live in today. Our growth has come from innovative, bold approaches to solving some of the world’s most challenging communication technology problems in the most efficient and effective manner.
MaxLinear began by developing the world’s first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn’t achieve the extremely high-performance requirements using CMOS, but we proved them wrong and achieved enduring global market leadership with our designs. Since then, we’ve developed a full line of products that drive 4G and 5G infrastructure; enable data center, metro and long-haul optical interconnects; bring 10Gbit to the home; power the IoT revolution; and enable robust and reliable communication in harsh industrial environments. Over the years, we’ve expanded through organic growth and through several acquisitions that have perfectly complemented our existing portfolio and enabled us to deliver complete end-to-end solutions in our target markets. One such example was the acquisition of Intel’s Home Gateway Platform Division that added Wi-Fi, Ethernet, and Broadband Gateway Processor SoC technology to our connected home portfolio creating a complete and scalable platform of connectivity and access solutions to fully address our customers’ needs.
Our headquarters are in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, California; Valencia, Spain; Bangalore, India; Munich, Germany; Israel; and Singapore.
We have approximately 1,200 employees, a substantial majority of whom have engineering degrees and include masters and Ph.D. graduates from many of the premiere universities around the world. Our employees thrive on innovation, outstanding execution, outside-the-box thinking, nimbleness, and collaboration. Together, we form a high-energy business team that is focused on building the best and most innovative products on the market.
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Find Digital Design Engineer JobsDigital Design Engineer Job Market
Who's Hiring
- Meta14
- Apple13
- Raytheon8
- Texas Instruments8
- Synopsys7
Top Industries Hiring
- Technology & Software13
- Electronics & Hardware13
- Consulting & Professional Services5
- Education2
- Science & Research2
What Employers Look For
The qualifications that appear most often in digital design engineer jobs.
- Proficiency in SystemVerilog or VHDL for RTL design and simulation
- Experience with industry-standard EDA tools such as Synopsys or Cadence
- Bachelor's degree in electrical engineering, computer engineering, or a related field
- Hands-on experience with FPGA or ASIC design and implementation
- Familiarity with logic synthesis, timing closure, and static timing analysis
- Understanding of verification methodologies including UVM or formal verification
Tips for Your Digital Design Engineer Job Search
Tailor your resume to tapeout milestones
Hiring managers for digital design roles want to see completed silicon or FPGA deployments, not just project descriptions. List specific tapeout dates, process nodes, and your contribution at each stage so reviewers can quickly assess your hands-on depth.
Apply early to roles that fit
Migrate Mate lists digital design engineer openings from across the United States in one place, so you can find roles that match and apply directly to each listing.
Match your RTL language to the posting
Many digital design engineer openings specify SystemVerilog, VHDL, or both. When a job listing calls out a primary HDL, mirror that exact term in your resume summary and skills section to pass automated screening before a human reviews it.
Target postings by design abstraction level
Job descriptions vary widely from RTL coding to microarchitecture definition to physical-aware design. Filter your search by the abstraction level you work at so you avoid roles that are really layout or verification jobs with similar titles.
Prepare a simulation-focused portfolio piece
Bring a waveform screenshot or functional coverage report to interviews as a concrete artifact. Interviewers at IC companies regularly ask candidates to walk through a debug session, and having a real example ready shifts the conversation to your actual problem-solving process.
Negotiate start date around tape-in cycles
Many digital design teams are deadline-driven by tapeout schedules. When discussing your start date, ask about the current project phase. Joining at the RTL freeze stage rather than mid-verification gives you more room to onboard and contribute meaningfully from day one.
Digital Design Engineer Jobs: Frequently Asked Questions
Which companies are hiring the most digital design engineers?
The companies hiring the most digital design engineers right now include Meta, Apple, and Raytheon, with the largest share of openings in California, Texas, and New York, based on current listings on Migrate Mate as of November 2026. Semiconductor fabless companies and aerospace defense contractors consistently represent a large portion of active postings.
How many digital design engineer jobs are remote?
About 46% of digital design engineer openings are fully remote or hybrid as of November 2026, though the share varies significantly by specialization. FPGA firmware roles and architecture definition positions tend to offer more remote flexibility, while tapeout-intensive ASIC roles more often require on-site access to lab equipment and EDA tool servers.
How do you become a digital design engineer?
Start with a bachelor's degree in electrical or computer engineering, with coursework in digital logic, computer architecture, and HDL programming. Build hands-on experience through FPGA projects or academic tapeout programs. Develop fluency in SystemVerilog and at least one EDA toolchain, then pursue roles at IC design companies or defense contractors where you can work on full RTL-to-synthesis flows.
How do you get hired as a digital design engineer with little experience?
Focus on demonstrable projects rather than credentials. Build an open-source FPGA design on a development board, document your RTL code publicly, and walk through it in applications. Many companies hire new graduates specifically for FPGA prototyping or block-level RTL roles that require strong fundamentals but not prior tapeout experience, making these good entry points into the field.
What does the digital design engineer interview process look like?
Most processes start with a technical phone screen covering digital logic fundamentals, state machine design, and HDL syntax. That is typically followed by a design exercise where you write and simulate RTL live or take home a coding assignment. Final rounds usually include a system design discussion with senior engineers and a behavioral interview, with the full process often running across several weeks.
Where can I find and apply to digital design engineer jobs?
You can find and apply to digital design engineer jobs on Migrate Mate, which lists current openings from across the United States. Search the listings to find roles that match your HDL expertise, preferred industry, and experience level, then apply directly to each position that fits.
See All 272+ Digital Design Engineer Jobs
Find roles that match your experience and apply in just a few clicks.
Find Digital Design Engineer Jobs