Physical Design Engineer Jobs in Oregon
Physical Design Engineer jobs in Oregon are concentrated in the semiconductor and consumer electronics sectors, with steady demand for professionals at every level from new-grad RTL-to-GDSII contributors to senior timing closure and floorplan leads. The heaviest hiring is in Hillsboro, Beaverton, and Portland, where established names like Intel, Lattice Semiconductor, and Synopsys maintain significant engineering operations. The most sought-after specialties in Oregon include static timing analysis, place-and-route, and low-power design for advanced process nodes. See the openings below and apply to the ones that match your experience.
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Showing 5 of 12+ Physical Design Engineer jobs
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.
The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the CSME team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for experienced engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Senior Physical Design Verification Engineer to join the team to support our mission and culture. This key role will impact the organization by helping deliver cutting edge silicon.
#SCHIE #CSME
Responsibilities
- Work closely with top level and block level Physical Design Engineers on analysis and fixes on LVS, DRC, ERC, Antenna, etc.
- Drive full chip integration for physical design verification, signoff and Tape-outs on the leading-edge technology nodes.
- Collaborating with clock, analog, integration team on definition, implementation, and verification of critical chip routing, power delivery, block integration and other aspects.
- Work with 3pIP and 1pIP teams for efficient and timely SOC-IP handshake.
- Work with CAD team, tool vendors, foundry and other external partners to develop and validate new tools, flows, runsets, etc.
- Utilize scripting/AI skills to write and customize tool flows to maximize design efficiency and productivity.
Qualifications
Required Qualifications:
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Other Requirements:
- Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
- This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred Qualifications:
- BS/MS in Electrical or Computer Engineering/Electrical Engineering
- 5+ years of experience in semiconductor chip design/SOC physical design.
- Experience in Physical Verification EDA tools like Mentor Calibre and Synopsys ICV.
- Debugging skills for DRC, LVS, ERC, Antenna, High Voltage DRC, ESD, etc.
- Multiple SOC Tape-Out experience in the advanced foundry process nodes.
- Understanding of full chip integration, floor planning, IO RDL and bump planning.
- Experience and knowledge of physical design flow and industry standard PNR tool (Fusion Compiler/Innovus, ICC2, etc.)
- Understanding of transistor/device basics.
- Proficient in scripting languages such as Perl, TCL, Python.
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process.
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.
The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the CSME team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for experienced engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Senior Physical Design Verification Engineer to join the team to support our mission and culture. This key role will impact the organization by helping deliver cutting edge silicon.
#SCHIE #CSME
Responsibilities
- Work closely with top level and block level Physical Design Engineers on analysis and fixes on LVS, DRC, ERC, Antenna, etc.
- Drive full chip integration for physical design verification, signoff and Tape-outs on the leading-edge technology nodes.
- Collaborating with clock, analog, integration team on definition, implementation, and verification of critical chip routing, power delivery, block integration and other aspects.
- Work with 3pIP and 1pIP teams for efficient and timely SOC-IP handshake.
- Work with CAD team, tool vendors, foundry and other external partners to develop and validate new tools, flows, runsets, etc.
- Utilize scripting/AI skills to write and customize tool flows to maximize design efficiency and productivity.
Qualifications
Required Qualifications:
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Other Requirements:
- Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
- This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred Qualifications:
- BS/MS in Electrical or Computer Engineering/Electrical Engineering
- 5+ years of experience in semiconductor chip design/SOC physical design.
- Experience in Physical Verification EDA tools like Mentor Calibre and Synopsys ICV.
- Debugging skills for DRC, LVS, ERC, Antenna, High Voltage DRC, ESD, etc.
- Multiple SOC Tape-Out experience in the advanced foundry process nodes.
- Understanding of full chip integration, floor planning, IO RDL and bump planning.
- Experience and knowledge of physical design flow and industry standard PNR tool (Fusion Compiler/Innovus, ICC2, etc.)
- Understanding of transistor/device basics.
- Proficient in scripting languages such as Perl, TCL, Python.
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process.
See All 12 Physical Design Engineer Jobs in Oregon
Find roles in Oregon that match your experience and apply in just a few clicks.
Find Physical Design Engineer JobsPhysical Design Engineer Jobs by City in Oregon
Where Oregon roles are concentrated, by current openings.
Physical Design Engineer Job Market in Oregon
A snapshot from current Oregon openings, updated as new roles post.
Who's Hiring
Top Industries Hiring
- Electronics & Hardware
What Oregon Employers Look For
The qualifications that appear most often in physical design engineer jobs across Oregon.
- Bachelor's or master's degree in electrical engineering or a related technical field
- Hands-on experience with place-and-route tools such as Cadence Innovus or Synopsys IC Compiler
- Proficiency in static timing analysis and timing closure on advanced process nodes
- Familiarity with low-power design techniques including clock gating and power domains
- Experience writing and debugging physical design scripts in Tcl or Python
- Strong understanding of DRC, LVS, and signoff flows used in tape-out processes
Physical Design Engineer Jobs in Oregon: Frequently Asked Questions
How do you become a physical design engineer in Oregon?
Physical design engineering in Oregon does not require a state-issued license. The standard path is a bachelor's or master's degree in electrical engineering or computer engineering, followed by hands-on experience with industry-standard EDA tools. Oregon's semiconductor-heavy market, anchored in the Hillsboro and Beaverton corridor, means most entry-level candidates enter through large chipmaker rotational programs or graduate recruiting pipelines at companies operating fabrication and design centers in the state.
Which companies hire physical design engineers in Oregon?
Employers hiring physical design engineers in Oregon right now include Apple, Microsoft, and Intel Corporation, based on current listings on Migrate Mate as of November 2026. Oregon's concentration of semiconductor fabs and design centers, particularly in Washington County, makes it one of the more active states for this role outside of California.
Which Oregon cities have the most physical design engineer jobs?
Beaverton and Hillsboro account for the largest share of physical design engineer openings in Oregon. Hillsboro and Beaverton dominate because Intel's large campus and several adjacent semiconductor design firms are headquartered or anchored there, while Portland draws openings from fabless design shops and EDA tool vendors with regional offices in the metro.
Are there remote physical design engineer jobs in Oregon?
Yes, but they are relatively limited. Physical design work often requires access to licensed EDA tools, secure compute environments, and close collaboration with verification and layout teams, which keeps many roles on-site or hybrid. About 50% of physical design engineer openings tied to Oregon are remote or hybrid as of November 2026. The portions of the role most compatible with remote work include timing analysis scripting and signoff review rather than hands-on floorplanning sessions.
How can I get hired as a physical design engineer in Oregon with little or no experience?
The most realistic entry path is through a new-graduate or university-hire program at one of Oregon's large chipmakers. Intel's campus in Hillsboro regularly recruits graduating electrical and computer engineering students into rotational technical programs that include physical design exposure. Candidates without direct experience can also move laterally from adjacent roles in digital verification, layout QA, or FPGA design. Building a portfolio that demonstrates tool proficiency in place-and-route or timing analysis, even through academic projects or open-source PDK work, gives applicants a concrete edge in screening.
Where can I find and apply to physical design engineer jobs in Oregon?
You can find and apply to physical design engineer jobs in Oregon on Migrate Mate, which lists current Oregon openings. Search the roles that fit your experience level and specialization, then apply directly to the ones that match.
See All 12 Physical Design Engineer Jobs in Oregon
Find roles in Oregon that match your experience and apply in just a few clicks.
Find Physical Design Engineer Jobs