Physical Design Engineer Jobs in Oregon
Physical Design Engineer jobs in Oregon are concentrated in the semiconductor and consumer electronics sectors, with steady demand for professionals at every level from new-grad RTL-to-GDSII contributors to senior timing closure and floorplan leads. The heaviest hiring is in Hillsboro, Beaverton, and Portland, where established names like Intel, Lattice Semiconductor, and Synopsys maintain significant engineering operations. The most sought-after specialties in Oregon include static timing analysis, place-and-route, and low-power design for advanced process nodes. See the openings below and apply to the ones that match your experience.
Find Physical Design Engineer JobsOverview
Showing 5 of 8+ Physical Design Engineer jobs
In this highly visible role, you will be responsible for implementing complete chip design from netlist to tapeout.
Description
- Work with the FE team to understand chip architecture and drive physical aspects early in the design cycle.
- Work with the physical design team to drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress.
- Be a focal point for place and route, drive the work among place and route engineers, set goals and milestones, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route.
- Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.
Preferred Qualifications
Needs to be familiar with aspects of ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration.
Experience with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
Familiar with a hierarchical design approach, top-down design, budgeting, timing and physical convergence.
Experience integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain is required.
Experience with large SoC designs (>20M gates) with frequencies in excess of 1GHz using innovative sub 45nm technologies.
A detailed understanding of database management issues is required.
From a CAD tool perspective, experience with floorplanning tools, P&R flows, global timing verification and physical design verification flows is required.
Familiar with various process-related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,000 and $308,500, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
In this highly visible role, you will be responsible for implementing complete chip design from netlist to tapeout.
Description
- Work with the FE team to understand chip architecture and drive physical aspects early in the design cycle.
- Work with the physical design team to drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress.
- Be a focal point for place and route, drive the work among place and route engineers, set goals and milestones, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route.
- Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.
Preferred Qualifications
Needs to be familiar with aspects of ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration.
Experience with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
Familiar with a hierarchical design approach, top-down design, budgeting, timing and physical convergence.
Experience integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain is required.
Experience with large SoC designs (>20M gates) with frequencies in excess of 1GHz using innovative sub 45nm technologies.
A detailed understanding of database management issues is required.
From a CAD tool perspective, experience with floorplanning tools, P&R flows, global timing verification and physical design verification flows is required.
Familiar with various process-related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,000 and $308,500, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
See All 8 Physical Design Engineer Jobs in Oregon
Find roles in Oregon that match your experience and apply in just a few clicks.
Find Physical Design Engineer JobsPhysical Design Engineer Jobs by City in Oregon
Where Oregon roles are concentrated, by current openings.
Physical Design Engineer Job Market in Oregon
A snapshot from current Oregon openings, updated as new roles post.
Who's Hiring
Top Industries Hiring
- Electronics & Hardware
- Technology & Software
- Construction & Real Estate
- Consulting & Professional Services
What Oregon Employers Look For
The qualifications that appear most often in physical design engineer jobs across Oregon.
- Bachelor's or master's degree in electrical engineering or a related technical field
- Hands-on experience with place-and-route tools such as Cadence Innovus or Synopsys IC Compiler
- Proficiency in static timing analysis and timing closure on advanced process nodes
- Familiarity with low-power design techniques including clock gating and power domains
- Experience writing and debugging physical design scripts in Tcl or Python
- Strong understanding of DRC, LVS, and signoff flows used in tape-out processes
Physical Design Engineer Jobs in Oregon: Frequently Asked Questions
How do you become a physical design engineer in Oregon?
Physical design engineering in Oregon does not require a state-issued license. The standard path is a bachelor's or master's degree in electrical engineering or computer engineering, followed by hands-on experience with industry-standard EDA tools. Oregon's semiconductor-heavy market, anchored in the Hillsboro and Beaverton corridor, means most entry-level candidates enter through large chipmaker rotational programs or graduate recruiting pipelines at companies operating fabrication and design centers in the state.
Which companies hire physical design engineers in Oregon?
Employers hiring physical design engineers in Oregon right now include Apple, Microsoft, and Intel Corporation, based on current listings on Migrate Mate as of September 2026. Oregon's concentration of semiconductor fabs and design centers, particularly in Washington County, makes it one of the more active states for this role outside of California.
Which Oregon cities have the most physical design engineer jobs?
Hillsboro, Beaverton, and Portland account for the largest share of physical design engineer openings in Oregon. Hillsboro and Beaverton dominate because Intel's large campus and several adjacent semiconductor design firms are headquartered or anchored there, while Portland draws openings from fabless design shops and EDA tool vendors with regional offices in the metro.
Are there remote physical design engineer jobs in Oregon?
Yes, but they are relatively limited. Physical design work often requires access to licensed EDA tools, secure compute environments, and close collaboration with verification and layout teams, which keeps many roles on-site or hybrid. About 67% of physical design engineer openings tied to Oregon are remote or hybrid as of September 2026. The portions of the role most compatible with remote work include timing analysis scripting and signoff review rather than hands-on floorplanning sessions.
How can I get hired as a physical design engineer in Oregon with little or no experience?
The most realistic entry path is through a new-graduate or university-hire program at one of Oregon's large chipmakers. Intel's campus in Hillsboro regularly recruits graduating electrical and computer engineering students into rotational technical programs that include physical design exposure. Candidates without direct experience can also move laterally from adjacent roles in digital verification, layout QA, or FPGA design. Building a portfolio that demonstrates tool proficiency in place-and-route or timing analysis, even through academic projects or open-source PDK work, gives applicants a concrete edge in screening.
Where can I find and apply to physical design engineer jobs in Oregon?
You can find and apply to physical design engineer jobs in Oregon on Migrate Mate, which lists current Oregon openings. Search the roles that fit your experience level and specialization, then apply directly to the ones that match.
See All 8 Physical Design Engineer Jobs in Oregon
Find roles in Oregon that match your experience and apply in just a few clicks.
Find Physical Design Engineer Jobs