Physical Design Engineer Jobs in Texas
Physical Design Engineer jobs in Texas are among the most active in the country, concentrated in semiconductor manufacturing, defense electronics, and consumer chip design across Austin, Dallas, and San Jose-adjacent design centers operating from Texas soil. Major employers with deep, lasting roots here include Texas Instruments, NXP Semiconductors, and Samsung Semiconductor's Austin fab. Demand runs from junior layout engineers through principal physical implementation leads, with the sharpest need in timing closure, place-and-route, and power integrity. See the openings below and apply to the ones that match your experience.
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About Positron AI
Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Chips built for the training era keep running into two walls at inference time: memory bandwidth and chip-to-chip networking. We designed our architecture to break through both. Our first-generation Atlas systems are deploying in Oracle Cloud Infrastructure. Asimov, our first custom ASIC, takes that architecture to silicon. In simulations, Asimov delivers several times more tokens per dollar and tokens per watt than leading GPUs, at a fraction of the power. Paired in our Titan system, Asimov is built to serve models beyond 16 trillion parameters. In September 2026, we raised $875 million at a $5 billion valuation. NEA led the round, joined by Atreides Management, Valor Equity Partners, and others, to bring Asimov and Titan to market. Our team includes engineers from Groq, Lambda, NVIDIA, Meta, F5, and many other industry leaders.
Role Overview
As Senior DFT Engineer, you'll own DFT implementation end-to-end: defining the DFT micro-architecture for our accelerators, developing and integrating it into internal RTL and third-party IP, driving implementation with our backend design partner, and ensuring high-quality silicon bring-up through comprehensive pre-silicon validation. This is a hands-on, technical ownership role from definition through tapeout and into first silicon, not a coordination role.
Key Responsibilities
- Micro-architect and implement DFT instrumentation logic, including scan insertion, compression, ATPG, memory BIST, boundary scan (IEEE 1149.x), IJTAG (IEEE 1687) infrastructure, and debug/observability features.
- Integrate DFT IP into internally developed RTL, and evaluate and integrate DFT capabilities from third-party IP providers.
- Work directly in RTL, synthesis, and DFT tool flows.
- Develop comprehensive DFT verification plans and validate DFT functionality through simulation and gate-level verification.
- Drive stuck-at, transition, cell-aware, and power-aware ATPG strategies, ensuring DFx coverage targets are achieved before tapeout.
- Work closely with backend implementation teams to ensure successful physical realization of the DFT architecture.
- Guide scan chain partitioning, compression planning, and test clock architecture.
- Address power-aware test implementation, timing closure considerations, and test mode integration.
- Partner closely with RTL design, design verification, physical design, package and test engineering, firmware, system software, and silicon validation to ensure DFT solutions are correct, compliant, complete, and consistent through silicon bring-up.
- Leverage modern AI tools to improve engineering productivity, including automated review of DFT reports, ATPG and coverage analysis, regression triage, documentation generation, workflow automation, and agentic engineering assistants.
Required Qualifications
- A BS, MS, or PhD in Electrical Engineering or Computer Engineering.
- 8+ years of ASIC development experience.
- Extensive hands-on DFT implementation experience on complex SoCs, with multiple successful production tapeouts.
- Deep understanding of scan architectures and their implementation, including ATPG, memory BIST (including repair), boundary scan, IJTAG, EDT, various fault models, and structural coverage analysis.
- Hands-on experience with Siemens Tessent DFT solutions (SSN, EDT, MBIST, RTLpro, Scanpro, Tessent Diagnosis) is required.
- Strong RTL design skills using Verilog/SystemVerilog.
- Practical experience with synthesis and gate-level verification.
- Strong scripting ability in Python, Tcl, Perl, or similar languages.
- Excellent debugging skills across RTL, netlists, and silicon failure analysis.
- A demonstrated ability to drive technical execution across cross-functional engineering teams.
Preferred Qualifications
- Experience with high-performance AI accelerators, GPUs, CPUs, networking ASICs, PCIe, HBM, LPDDR, or chiplet architectures.
- Exposure to high-speed SerDes and advanced process nodes (5nm and below).
- Background in low-power design, yield enhancement methodologies, and manufacturing test optimization.
- Hands-on experience with silicon bring-up, failure analysis, and post-silicon debug.
- A solid grasp of secure manufacturing and DFT, including the interaction between secure boot, hardware root of trust, scan access control, fuse programming, key management, and production test.
- Experience architecting in-system debug and observability infrastructure (trace, event logging, test registers, scan visibility) that accelerates emulation and first-silicon bring-up.
- Familiarity with emulation and pre-silicon validation platforms such as Palladium, ZeBu, Veloce, or FPGA prototyping to validate DFT features before tapeout.
Leveling & Scope
While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.
Why Join Us?
- Own DFT for a purpose-built AI inference accelerator from architecture definition through first silicon, with your decisions shaping Asimov and every generation that follows.
- Join a small, senior hardware team where your work directly determines silicon quality, yield, and time to market for frontier AI workloads.
Compensation & Benefits
Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.
At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity, and individual impact.
Benefits & Perks
- Fully company-paid medical, dental, and vision insurance for you and your dependents
- Company-paid life and disability coverage, with voluntary options to add more
- Supplemental hospital, critical illness, and accident coverage available
- Unlimited paid time off; we encourage everyone to truly unplug and recharge
- 13 paid company holidays
- Remote-first culture with a company-provided computer and home office setup
- Competitive salary and equity
- 401(k) with company matching, eligible from day one
Visa Support
Equal Opportunity Employer. If you're excited about the role but don't meet every bullet, we'd still love to hear from you.
About Positron AI
Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Chips built for the training era keep running into two walls at inference time: memory bandwidth and chip-to-chip networking. We designed our architecture to break through both. Our first-generation Atlas systems are deploying in Oracle Cloud Infrastructure. Asimov, our first custom ASIC, takes that architecture to silicon. In simulations, Asimov delivers several times more tokens per dollar and tokens per watt than leading GPUs, at a fraction of the power. Paired in our Titan system, Asimov is built to serve models beyond 16 trillion parameters. In September 2026, we raised $875 million at a $5 billion valuation. NEA led the round, joined by Atreides Management, Valor Equity Partners, and others, to bring Asimov and Titan to market. Our team includes engineers from Groq, Lambda, NVIDIA, Meta, F5, and many other industry leaders.
Role Overview
As Senior DFT Engineer, you'll own DFT implementation end-to-end: defining the DFT micro-architecture for our accelerators, developing and integrating it into internal RTL and third-party IP, driving implementation with our backend design partner, and ensuring high-quality silicon bring-up through comprehensive pre-silicon validation. This is a hands-on, technical ownership role from definition through tapeout and into first silicon, not a coordination role.
Key Responsibilities
- Micro-architect and implement DFT instrumentation logic, including scan insertion, compression, ATPG, memory BIST, boundary scan (IEEE 1149.x), IJTAG (IEEE 1687) infrastructure, and debug/observability features.
- Integrate DFT IP into internally developed RTL, and evaluate and integrate DFT capabilities from third-party IP providers.
- Work directly in RTL, synthesis, and DFT tool flows.
- Develop comprehensive DFT verification plans and validate DFT functionality through simulation and gate-level verification.
- Drive stuck-at, transition, cell-aware, and power-aware ATPG strategies, ensuring DFx coverage targets are achieved before tapeout.
- Work closely with backend implementation teams to ensure successful physical realization of the DFT architecture.
- Guide scan chain partitioning, compression planning, and test clock architecture.
- Address power-aware test implementation, timing closure considerations, and test mode integration.
- Partner closely with RTL design, design verification, physical design, package and test engineering, firmware, system software, and silicon validation to ensure DFT solutions are correct, compliant, complete, and consistent through silicon bring-up.
- Leverage modern AI tools to improve engineering productivity, including automated review of DFT reports, ATPG and coverage analysis, regression triage, documentation generation, workflow automation, and agentic engineering assistants.
Required Qualifications
- A BS, MS, or PhD in Electrical Engineering or Computer Engineering.
- 8+ years of ASIC development experience.
- Extensive hands-on DFT implementation experience on complex SoCs, with multiple successful production tapeouts.
- Deep understanding of scan architectures and their implementation, including ATPG, memory BIST (including repair), boundary scan, IJTAG, EDT, various fault models, and structural coverage analysis.
- Hands-on experience with Siemens Tessent DFT solutions (SSN, EDT, MBIST, RTLpro, Scanpro, Tessent Diagnosis) is required.
- Strong RTL design skills using Verilog/SystemVerilog.
- Practical experience with synthesis and gate-level verification.
- Strong scripting ability in Python, Tcl, Perl, or similar languages.
- Excellent debugging skills across RTL, netlists, and silicon failure analysis.
- A demonstrated ability to drive technical execution across cross-functional engineering teams.
Preferred Qualifications
- Experience with high-performance AI accelerators, GPUs, CPUs, networking ASICs, PCIe, HBM, LPDDR, or chiplet architectures.
- Exposure to high-speed SerDes and advanced process nodes (5nm and below).
- Background in low-power design, yield enhancement methodologies, and manufacturing test optimization.
- Hands-on experience with silicon bring-up, failure analysis, and post-silicon debug.
- A solid grasp of secure manufacturing and DFT, including the interaction between secure boot, hardware root of trust, scan access control, fuse programming, key management, and production test.
- Experience architecting in-system debug and observability infrastructure (trace, event logging, test registers, scan visibility) that accelerates emulation and first-silicon bring-up.
- Familiarity with emulation and pre-silicon validation platforms such as Palladium, ZeBu, Veloce, or FPGA prototyping to validate DFT features before tapeout.
Leveling & Scope
While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.
Why Join Us?
- Own DFT for a purpose-built AI inference accelerator from architecture definition through first silicon, with your decisions shaping Asimov and every generation that follows.
- Join a small, senior hardware team where your work directly determines silicon quality, yield, and time to market for frontier AI workloads.
Compensation & Benefits
Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.
At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity, and individual impact.
Benefits & Perks
- Fully company-paid medical, dental, and vision insurance for you and your dependents
- Company-paid life and disability coverage, with voluntary options to add more
- Supplemental hospital, critical illness, and accident coverage available
- Unlimited paid time off; we encourage everyone to truly unplug and recharge
- 13 paid company holidays
- Remote-first culture with a company-provided computer and home office setup
- Competitive salary and equity
- 401(k) with company matching, eligible from day one
Visa Support
Equal Opportunity Employer. If you're excited about the role but don't meet every bullet, we'd still love to hear from you.
See All 54 Physical Design Engineer Jobs in Texas
Find roles in Texas that match your experience and apply in just a few clicks.
Find Physical Design Engineer JobsPhysical Design Engineer Jobs by City in Texas
Where Texas roles are concentrated, by current openings.
Physical Design Engineer Job Market in Texas
A snapshot from current Texas openings, updated as new roles post.
Who's Hiring
- Apple23
- Qualcomm10
- Amazon Web Services3
- Meta2
- SpaceX2
Top Industries Hiring
- Electronics & Hardware11
- Technology & Software4
- Telecommunications3
- Aerospace & Defense1
- Media & Entertainment1
What Texas Employers Look For
The qualifications that appear most often in physical design engineer jobs across Texas.
- Bachelor's degree in electrical engineering, computer engineering, or closely related field required
- Proficiency in industry-standard EDA tools such as Cadence Innovus or Synopsys ICC2
- Hands-on experience with place-and-route, floorplanning, and timing closure at advanced nodes
- Familiarity with static timing analysis, power analysis, and DRC or LVS signoff flows
- Strong understanding of CMOS process technology and physical verification methodologies
- Experience with scripting languages such as Tcl or Python to automate layout and signoff tasks
Physical Design Engineer Jobs in Texas: Frequently Asked Questions
How do you become a physical design engineer in Texas?
Most physical design engineers in Texas enter the field with a bachelor's degree in electrical or computer engineering, though many senior roles expect a master's degree. The role carries no state-issued license in Texas. Employers do expect demonstrated fluency in commercial EDA toolsets and, for certain defense-adjacent positions at Texas contractors, the ability to obtain a federal security clearance. Building a portfolio of tape-out experience through university coursework, internships, or open-source chip projects strengthens candidacy considerably.
Which companies hire physical design engineers in Texas?
Texas physical design engineer roles are posted by Apple, Qualcomm, and Amazon Web Services and others right now, based on current listings on Migrate Mate as of November 2026. Texas's concentration of semiconductor headquarters and large fab operations means hiring tends to be sustained rather than episodic, with Austin and Dallas-area design centers posting positions across multiple seniority levels throughout the year.
Which Texas cities have the most physical design engineer jobs?
Austin, Richardson, and Dallas account for the largest share of physical design engineer openings in Texas. Austin anchors demand through the chip design divisions of Texas Instruments, Samsung Semiconductor, and a growing cluster of fabless startups, while Dallas draws engineers into telecom IC and defense electronics work, and other metro areas reflect the broader dispersal of embedded systems and EDA-dependent engineering teams across the state.
Are there remote physical design engineer jobs in Texas?
Yes, but they're relatively limited. Physical design work is tool-intensive and often tied to secure server environments or on-site EDA license servers, which constrains full-remote arrangements. About 14% of physical design engineer openings tied to Texas are remote or hybrid as of November 2026, with hybrid schedules more common than fully remote. Front-end design review and scripting tasks are most likely to appear in remote or partially remote postings.
How can I get hired as a physical design engineer in Texas with little or no experience?
The most realistic entry path is through a university new-graduate program at a major Texas semiconductor employer. Texas Instruments and NXP Semiconductors both run structured new-grad rotational programs from their Texas offices that place engineers into physical implementation teams. Candidates coming from adjacent roles in digital verification, ASIC design, or CAD support can often lateral in. Completing a full place-and-route flow on a university or open-source chip project and documenting it in a portfolio gives early-career applicants a concrete differentiator.
Where can I find and apply to physical design engineer jobs in Texas?
You can find and apply to physical design engineer jobs in Texas on Migrate Mate, which lists current Texas openings updated regularly. Search for roles that match your toolset and experience level, then apply directly to the ones that fit. No signup is required to see the listings.
See All 54 Physical Design Engineer Jobs in Texas
Find roles in Texas that match your experience and apply in just a few clicks.
Find Physical Design Engineer Jobs