Ic Design Engineer Jobs at Broadcom with Visa Sponsorship
Ic Design Engineer jobs at Broadcom sit at the core of its semiconductor and infrastructure hardware business, covering analog, mixed-signal, and digital design across high-volume product lines. Broadcom has a consistent track record of sponsoring work visas for this function, supporting candidates from offer stage through long-term permanent residency pathways.
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Broadcom is searching for a Physical Verification PD Engineer to join the Asic Products Division. This position involves working with the advanced nodes to continue driving next generation Artificial Intelligence and Machine Learning ecosystems through our PCIe Switch Products, while leading world class performance, through our Enterprise Products. More specifically, this position will require in-depth knowledge of Foundary rules, DFM and experience in silicon tape-out and respins.
Responsibilities:
- Execution of Chip level Physical Verification & Issue Resolution
- Work on setting up runsets for advance nodes and tool flows
- Manage and guide rules related to top level floorplan, I/O and bump planning
- Resolve physical design issues related to chip integration and assembly
- Provide technical direction on verification methodologies including DRC, LVS, ERC, and PERC
- Develop best practice guidelines for physical verification flows and runtime optimizations
Preferred qualifications:
- Bachelors's degree in Electrical Engineering and 8+ years of experience in physical design and verification
- Master's degree in Electrical Engineering and 6+ years of experience in physical design and verification
- Hands-on experience in running physical verification (LVS, DRC, ERC, PERC)
- Experience in parasitic extraction tools i.e. StarRC, Quantus
- Experience with EDA tools and flows such as ICV, Calibre and Pegasus EDA tools
- Rule deck coding experience in ICV, Calibre or Pegasus EDA tools
- Experience in resolving chip level DRC/LVS/EMIR issues for advance nodes and tape out experience
- Electrical Rule Checking (ERC/PERC): Analyze ESD (Electrostatic Discharge), latch-up, floating gates, and power-domain isolation vulnerabilities
- Density & Fill: Manage automated dummy metal, poly, and diffusion filling strategies to meet local and global density rules
- Yield Enhancement (DFM): Implement Design for Manufacturability fixes, including critical area analysis (CAA), via-doubling, and edge-displacement rules.
- Collaborate with physical design team to resolve critical top-level integration violations
- Experience in scripting languages like Python, Tcl, or Perl
- Excellent verbal and written communication skills
- Must work in person at our San Jose site and no remote work allowed
Compensation and Benefits
The annual base salary range for this position is To
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Job Description:
Broadcom is searching for a Physical Verification PD Engineer to join the Asic Products Division. This position involves working with the advanced nodes to continue driving next generation Artificial Intelligence and Machine Learning ecosystems through our PCIe Switch Products, while leading world class performance, through our Enterprise Products. More specifically, this position will require in-depth knowledge of Foundary rules, DFM and experience in silicon tape-out and respins.
Responsibilities:
- Execution of Chip level Physical Verification & Issue Resolution
- Work on setting up runsets for advance nodes and tool flows
- Manage and guide rules related to top level floorplan, I/O and bump planning
- Resolve physical design issues related to chip integration and assembly
- Provide technical direction on verification methodologies including DRC, LVS, ERC, and PERC
- Develop best practice guidelines for physical verification flows and runtime optimizations
Preferred qualifications:
- Bachelors's degree in Electrical Engineering and 8+ years of experience in physical design and verification
- Master's degree in Electrical Engineering and 6+ years of experience in physical design and verification
- Hands-on experience in running physical verification (LVS, DRC, ERC, PERC)
- Experience in parasitic extraction tools i.e. StarRC, Quantus
- Experience with EDA tools and flows such as ICV, Calibre and Pegasus EDA tools
- Rule deck coding experience in ICV, Calibre or Pegasus EDA tools
- Experience in resolving chip level DRC/LVS/EMIR issues for advance nodes and tape out experience
- Electrical Rule Checking (ERC/PERC): Analyze ESD (Electrostatic Discharge), latch-up, floating gates, and power-domain isolation vulnerabilities
- Density & Fill: Manage automated dummy metal, poly, and diffusion filling strategies to meet local and global density rules
- Yield Enhancement (DFM): Implement Design for Manufacturability fixes, including critical area analysis (CAA), via-doubling, and edge-displacement rules.
- Collaborate with physical design team to resolve critical top-level integration violations
- Experience in scripting languages like Python, Tcl, or Perl
- Excellent verbal and written communication skills
- Must work in person at our San Jose site and no remote work allowed
Compensation and Benefits
The annual base salary range for this position is To
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
See all Ic Design Engineer Jobs at Broadcom
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Get Access To All JobsTips for Finding Ic Design Engineer Jobs at Broadcom
Align your portfolio to Broadcom's product lines
Broadcom hires IC Design Engineers across networking ASICs, storage controllers, and broadband chips. Tailor your resume and portfolio to show tape-out experience or simulation work on designs that map directly to these product families, not general CMOS fundamentals.
Clarify your OPT or CPT timeline early
If you're on F-1 OPT, confirm your STEM extension eligibility before interviews. Broadcom's IC design hiring cycles can stretch several months, so your remaining OPT runway affects which roles and start dates are realistically on the table.
Verify E-Verify enrollment before accepting an offer
STEM OPT extensions require your employer to be enrolled in E-Verify. Confirm Broadcom's specific hiring entity on your offer letter is enrolled, since large semiconductor companies sometimes hire through subsidiaries with separate E-Verify registrations.
Understand how H-1B cap timing affects your start date
H-1B cap petitions must be filed in April for an October 1 start. If you receive a Broadcom offer after the April filing window, you'll need to bridge on OPT or another valid status until the following fiscal year cap opens.
Request clarity on PERM sponsorship timelines during negotiation
Broadcom sponsors EB-2 and EB-3 Green Cards for IC Design Engineers, but PERM labor certification processing through DOL can take a year or more before an I-140 is filed. Ask directly which employment category your role is being sponsored under.
Use Migrate Mate to filter roles by visa type before applying
Not every IC Design Engineer opening at Broadcom is posted with sponsorship details. Use Migrate Mate to filter Broadcom listings by the visa categories they support, so you're targeting roles where sponsorship is confirmed before you invest time in the process.
Frequently Asked Questions
Does Broadcom sponsor H-1B visas for IC Design Engineers?
Yes, Broadcom sponsors H-1B visas for IC Design Engineers. The company has an established process for filing H-1B cap petitions and has consistently supported this role through the sponsorship pathway. If you're currently on F-1 OPT, Broadcom can bridge your status until an H-1B visa becomes effective on October 1 following a successful lottery selection.
How do I apply for IC Design Engineer jobs at Broadcom?
Applications go through Broadcom's careers portal. Search for IC Design Engineer roles filtered by your area of specialization, such as analog, digital, or mixed-signal. Tailor your resume to the specific product line listed in the job description. You can also browse Broadcom's open IC Design Engineer positions with confirmed visa sponsorship on Migrate Mate before applying directly.
Which visa types does Broadcom commonly use for IC Design Engineers?
Broadcom sponsors H-1B visas for IC Design Engineers as the primary work authorization pathway. For candidates already in the U.S. on F-1 status, F-1 OPT and F-1 CPT are used during early employment. For longer-term permanent residency, Broadcom supports EB-2 and EB-3 Green Card sponsorship, and TN visas are available for Canadian and Mexican nationals in qualifying roles.
What qualifications does Broadcom expect for IC Design Engineer roles?
Most IC Design Engineer positions at Broadcom require a bachelor's degree in electrical engineering or a closely related field, with a master's or PhD preferred for senior or research-focused roles. Hands-on experience with industry-standard EDA tools, tape-out experience, and familiarity with high-speed or low-power design are commonly listed requirements. Broadcom's H-1B petitions typically classify these roles as specialty occupations requiring the specific degree field.
How long does the visa sponsorship process take at Broadcom for IC Design Engineers?
For H-1B sponsorship, Broadcom must file during the April cap season for an October 1 start, so your offer timing relative to that window matters significantly. PERM labor certification for Green Card sponsorship through DOL typically adds a year or more before the I-140 petition stage. Building buffer into your timeline, especially around F-1 OPT expiration, is essential for avoiding gaps in work authorization.