E-3 Visa Senior Physical Design Engineer Jobs
Senior Physical Design Engineer roles in semiconductors and chip design qualify as E-3 visa specialty occupations, making Australian engineers eligible for U.S. work visa sponsorship without competing in the H-1B lottery. The E-3 visa has no annual cap, requires a bachelor's degree in electrical engineering or a related field, and renews in two-year increments indefinitely.
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Get Access To All JobsINTRODUCTION
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google’s Tensor Processing Units (TPUs) are incredibly complex, pushing the boundaries of physical design, power, and performance. In this role, you will provide technical leadership for the physical design of our next-generation AI silicon. Because of the sheer scale of our chips, our physical design leadership is highly dynamic; you will be expected to drive end-to-end execution with a scope that scales from owning highly complex, critical macro-subsystems up to overarching project-wide top-level implementation, depending on project needs.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google.
ROLE AND RESPONSIBILITIES
- Lead the physical design implementation and strategy for high-performance silicon, with leadership scope ranging from critical, high-complexity subchips to overarching top-level execution based on project phases and team needs.
- Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
- Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
- Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
- Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.
MINIMUM QUALIFICATIONS
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with physical design and leading full-chip or massively intricate subchip implementation (e.g., from RTL2GDSII, including key stages like floorplanning, place and route, and timing closure) for high-speed ASICs in advanced process nodes.
- Experience in Python, Tcl, or Perl scripting.
PREFERRED QUALIFICATIONS
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with Cadence Innovus, Synopsys DP, Mentor Calibre, and StarRC, plus understanding of foundry technology files, rule decks, physical sign-off, and 2.5D/3D packaging.
- Technical leadership experience managing execution schedules, mitigating risks, and driving cross-functional collaboration with internal teams and external vendors.
- Understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
- Ability to navigate ambiguity, scale leadership across the physical design hierarchy, and excellent communication skills to articulate complex technical challenges to stakeholders.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
INTRODUCTION
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google’s Tensor Processing Units (TPUs) are incredibly complex, pushing the boundaries of physical design, power, and performance. In this role, you will provide technical leadership for the physical design of our next-generation AI silicon. Because of the sheer scale of our chips, our physical design leadership is highly dynamic; you will be expected to drive end-to-end execution with a scope that scales from owning highly complex, critical macro-subsystems up to overarching project-wide top-level implementation, depending on project needs.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google.
ROLE AND RESPONSIBILITIES
- Lead the physical design implementation and strategy for high-performance silicon, with leadership scope ranging from critical, high-complexity subchips to overarching top-level execution based on project phases and team needs.
- Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
- Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
- Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
- Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.
MINIMUM QUALIFICATIONS
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with physical design and leading full-chip or massively intricate subchip implementation (e.g., from RTL2GDSII, including key stages like floorplanning, place and route, and timing closure) for high-speed ASICs in advanced process nodes.
- Experience in Python, Tcl, or Perl scripting.
PREFERRED QUALIFICATIONS
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with Cadence Innovus, Synopsys DP, Mentor Calibre, and StarRC, plus understanding of foundry technology files, rule decks, physical sign-off, and 2.5D/3D packaging.
- Technical leadership experience managing execution schedules, mitigating risks, and driving cross-functional collaboration with internal teams and external vendors.
- Understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
- Ability to navigate ambiguity, scale leadership across the physical design hierarchy, and excellent communication skills to articulate complex technical challenges to stakeholders.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
See all 167+ E-3 Visa Senior Physical Design Engineer Jobs
Sign up for free to unlock all listings, filter by visa type, and get alerts for new E-3 Visa Senior Physical Design Engineer Jobs.
Get Access To All JobsTips for Finding E-3 Visa Sponsorship as a Senior Physical Design Engineer
Align your credentials to U.S. specialty occupation standards
Your Australian three-year bachelor's in electrical engineering is generally accepted as equivalent to a U.S. four-year degree for E-3 purposes. Get a credential evaluation from a NACES-recognized evaluator before applying so employers don't raise objections during LCA filing.
Target semiconductor companies with active LCA filings
Search the DOL's Office of Foreign Labor Certification disclosure data for companies that have filed LCAs for physical design, place-and-route, or timing closure roles. Repeat LCA filers already understand the process and won't need to be educated on E-3 sponsorship at the offer stage.
Clarify EDA tool expertise upfront in applications
Roles requiring Cadence Innovus, Synopsys IC Compiler, or Mentor Calibre are tightly scoped. Naming your specific tool stack in your resume signals specialty occupation depth and reduces the risk of an employer questioning whether the role meets DOL's bachelor's degree requirement for an LCA.
Confirm the employer will file the LCA before accepting an offer
Some hiring managers confuse the E-3 with a self-sponsored visa. Before you get deep into negotiations, confirm in writing that the employer will file the LCA with the DOL. The LCA must be certified before your consulate appointment, so this step cannot be skipped or delayed.
Use Migrate Mate's E-3 filing service to handle LCA and visa paperwork
Physical design offers often come with tight start dates. Migrate Mate's E-3 filing service manages the LCA submission, visa application documents, and consulate preparation end-to-end, so you're not coordinating between your employer's HR team and the DOL on your own.
Prepare for IP and export control questions at the consulate
Consular officers sometimes ask additional questions for engineering roles involving chip architecture or proprietary design methodologies, particularly if your employer works in defense-adjacent semiconductor markets. Have a plain-language description of your role ready that avoids classified or export-controlled terminology.
E-3 Visa Senior Physical Design Engineer: Frequently Asked Questions
Where can I find Senior Physical Design Engineer jobs that offer E-3 visa sponsorship?
Migrate Mate is built specifically for Australian professionals searching for U.S. roles with E-3 sponsorship. It surfaces Senior Physical Design Engineer positions at employers who are already set up to file LCAs, so you're not cold-applying to companies that have never sponsored an Australian engineer before.
How much does it cost to get an E-3 visa?
Migrate Mate's E-3 filing service covers the entire process for $499, including the Labor Condition Application, visa document preparation, and consulate appointment guidance. Traditional immigration lawyers charge $2,000–$5,000+ for the same work. The E-3 has less paperwork than most work visas, so paying thousands for legal help is usually unnecessary.
Does a Senior Physical Design Engineer role qualify as an E-3 specialty occupation?
Yes. Physical design engineering requires a bachelor's degree in electrical engineering, computer engineering, or a closely related field, and the work is sufficiently specialized to meet DOL's specialty occupation definition. The role's reliance on EDA tools, timing analysis, and physical verification methodologies supports the degree requirement. Your job offer letter should describe these responsibilities clearly to support the LCA.
How does the E-3 compare to the H-1B for Senior Physical Design Engineer roles?
The E-3 has no annual lottery and no numerical cap, so you can apply at any point in the year after receiving a job offer. The H-1B requires registration in a lottery held each spring, with selection rates well below 50% in recent years. For Australian engineers, the E-3 is a direct path that doesn't depend on chance. Both visas require an employer-filed LCA and a specialty occupation job offer.
Can I change employers on an E-3 while working as a Physical Design Engineer?
Yes, but the process restarts with each new employer. Your new employer must file a fresh LCA with the DOL and you'll need to attend a new consulate appointment to get an updated E-3 visa stamp before starting work, unless you're transferring status inside the U.S. There's no portability provision equivalent to AC21 for the E-3, so plan for a two-to-six-week transition window.