H-1B1 Chile Visa Design Lead Jobs
Design Lead jobs with H-1B1 Chile visa sponsorship are open to Chilean nationals under the U.S.-Chile Free Trade Agreement. No lottery, no USCIS petition, and the 1,400-visa annual cap rarely fills. You apply directly at the consulate once you have a certified LCA and a U.S. job offer.
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Get Access To All JobsMinimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience in physical design, including custom structured datapath implementation.
- Experience hardening dense compute units (such as dot-product engines, multiplier-accumulator (MACs), multipliers, or arithmetic logic unit (ALUs) into high-frequency, low-power macros.
- Experience in sub-7nm process nodes (including FinFET and Gate-All-Around architectures), managing the physical density and routing congestion typical of custom datapaths.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with focus on computer architecture.
- Experience in structured placement methodologies (e.g., relative placement, data-flow driven layout, and customized power-grid stitching for dense blocks).
- Experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation.
- Experience with physical design and timing, with managing PT-to-PnR timing correlations and metal-fill impacts on dense structures.
- Expert-level scripting versatility (Tcl, Python, Perl) to build layout automation and structural constraints within standard EDA tools.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will be empowering Google and our customers with breakthrough capabilities by delivering transformational, co-optimized silicon and technology leadership at scale. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Own critical custom datapath and matrix multiplication accumulator blocks, driving execution from RTL-to-GDSII including synthesis, floor-planning, place and route (PNR), timing closure, and physical signoff.
- Understand math-intensive micro-architecture to perform detailed feasibility studies, analyzing performance, power, and area (PPA) tradeoffs to achieve optimal design closure.
- Develop and improve advanced physical design methodologies and customize implementation recipes, specifically optimizing PPA across complex arithmetic pipeline structures. Manage different PNR tools - synopsys fusion compiler, cadence (Innovus/Genus), PrimeTime, StarRC, Calibre, Apache Redhawk.
- Implement and execute key design phases: floor-planning, synthesis, placement, clock tree synthesis (CTS), timing closure, routing, extraction, physical verification (design rule checking (DRC)/layout versus schematic (LVS), electromigration (EM)/IR, and final signoff.
- Lead sub-chip execution and drive delivery, providing direct technical guidance and mentorship to a small team of engineers to ensure on-schedule project completion.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience in physical design, including custom structured datapath implementation.
- Experience hardening dense compute units (such as dot-product engines, multiplier-accumulator (MACs), multipliers, or arithmetic logic unit (ALUs) into high-frequency, low-power macros.
- Experience in sub-7nm process nodes (including FinFET and Gate-All-Around architectures), managing the physical density and routing congestion typical of custom datapaths.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with focus on computer architecture.
- Experience in structured placement methodologies (e.g., relative placement, data-flow driven layout, and customized power-grid stitching for dense blocks).
- Experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation.
- Experience with physical design and timing, with managing PT-to-PnR timing correlations and metal-fill impacts on dense structures.
- Expert-level scripting versatility (Tcl, Python, Perl) to build layout automation and structural constraints within standard EDA tools.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will be empowering Google and our customers with breakthrough capabilities by delivering transformational, co-optimized silicon and technology leadership at scale. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Own critical custom datapath and matrix multiplication accumulator blocks, driving execution from RTL-to-GDSII including synthesis, floor-planning, place and route (PNR), timing closure, and physical signoff.
- Understand math-intensive micro-architecture to perform detailed feasibility studies, analyzing performance, power, and area (PPA) tradeoffs to achieve optimal design closure.
- Develop and improve advanced physical design methodologies and customize implementation recipes, specifically optimizing PPA across complex arithmetic pipeline structures. Manage different PNR tools - synopsys fusion compiler, cadence (Innovus/Genus), PrimeTime, StarRC, Calibre, Apache Redhawk.
- Implement and execute key design phases: floor-planning, synthesis, placement, clock tree synthesis (CTS), timing closure, routing, extraction, physical verification (design rule checking (DRC)/layout versus schematic (LVS), electromigration (EM)/IR, and final signoff.
- Lead sub-chip execution and drive delivery, providing direct technical guidance and mentorship to a small team of engineers to ensure on-schedule project completion.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
See all 104+ H-1B1 Chile Visa Design Lead Jobs
Sign up for free to unlock all listings, filter by visa type, and get alerts for new H-1B1 Chile Visa Design Lead Jobs.
Get Access To All JobsTips for Finding Design Lead Jobs
Audit your portfolio for U.S. specialty occupation standards
The H-1B1 visa requires your Design Lead role to qualify as a specialty occupation. Document the strategic and cross-functional scope of your work, system-level design decisions and team leadership, because purely executional roles can draw scrutiny at the consulate.
Check prevailing wage before negotiating your offer
Your employer's LCA must certify a wage at or above the DOL prevailing wage for Design Lead in the specific metro area. Run the OFLC Wage Search before you negotiate so your offer clears the DOL threshold without a last-minute revision.
Target employers with active LCA filing histories
Search Migrate Mate to filter Design Lead roles by employers who have already filed Labor Condition Applications for H-1B1 Chile sponsorship. Those employers already understand the consular filing process and are less likely to withdraw an offer mid-application.
Confirm your employer is E-Verify enrolled before signing
H-1B1 visa sponsorship requires the employer to participate in E-Verify. Ask HR directly before you accept an offer, many smaller studios or in-house design teams haven't enrolled, which disqualifies them as sponsors regardless of intent.
Request the LCA posting notice details in writing
DOL requires your employer to post the LCA notice at the worksite for ten consecutive business days before certification. Ask your employer to confirm the posting dates and worksite address in writing, you'll need this documentation if the consular officer questions the filing timeline.
Use your O*NET profile to preempt consular questions
Review the Design Lead occupation profile in O*NET before your visa interview. Consular officers may ask how your background maps to the listed knowledge and skills requirements. Aligning your answers to that profile makes the specialty occupation case concrete and hard to dispute.
Frequently Asked Questions
Does a Design Lead role qualify as a specialty occupation for the H-1B1 Chile visa?
Yes, if the role requires a bachelor's degree or higher in a directly related field such as design, architecture, human-computer interaction, or a closely aligned discipline. A generalist title that accepts any degree field is harder to support. Your employer's LCA and job description must reflect the specialized degree requirement, not just a preference for one.
How does the H-1B1 Chile visa compare to the H-1B for a Design Lead position?
The H-1B1 Chile visa skips the H-1B lottery entirely and is processed at the consulate rather than through USCIS. The 1,400-visa annual cap for Chilean nationals rarely fills, so timing isn't a constraint. The trade-off is that H-1B visa1 doesn't carry dual-intent protection, meaning you can't simultaneously pursue permanent residency on this status.
How do I find U.S. employers willing to sponsor a Design Lead on an H-1B1 Chile visa?
Migrate Mate lets you search specifically for Design Lead roles at employers with verified H-1B1 Chile LCA filing history, so you're targeting companies that already understand and have executed the sponsorship process. That narrows the field to employers who won't require internal HR education before they commit to your application.
What documents should I prepare before the consular interview for a Design Lead H-1B1 Chile application?
Bring your certified LCA, the original job offer letter specifying your title and duties, educational credentials showing your degree aligns with the specialty occupation, and your DS-160 confirmation. If your degree is from a Chilean university, have an equivalency evaluation ready. The consular officer may also ask for portfolio evidence that your role is genuinely design-leadership, not production work.
Can I switch to a different Design Lead role at a new employer while on H-1B1 Chile status?
Yes, but your new employer must file a fresh LCA with DOL and you'll need to apply for a new H-1B1 visa at the consulate before starting work. Unlike H-1B, there's no portability provision under H-1B1 Chile, so you can't begin the new role while the paperwork is pending. Plan the transition timeline around consulate appointment availability.